Intel Itanium 9320 LW80603002550AB ユーザーズマニュアル
製品コード
LW80603002550AB
Intel
®
Itanium
®
Processor 9300 Series Datasheet
39
Electrical Specifications
VccArarat(12 V) is the input voltage to the Ararat regulator. The VCCA supply is used to
power the processor’s analog circuits. VCCIO is used to power the I/O circuits and the
QR (power and thermal management) unit. Once VCCIO is up and stable the external
environment can generate the SYSINT clock signals. Once the SYSINT clocks are valid
the external environment can assert the VROUTPUT_ENABLE signal. After
VROUTPUT_ENABLE is asserted the sequence of powering up the VCCUNCORE,
VCCCORE and VCCCACHE supplies begins. The VCCUNCORE, VCCCORE and VCCCACHE
supplies power the remainder of the sysint, the cores and the large cache arrays,
respectively.
power the processor’s analog circuits. VCCIO is used to power the I/O circuits and the
QR (power and thermal management) unit. Once VCCIO is up and stable the external
environment can generate the SYSINT clock signals. Once the SYSINT clocks are valid
the external environment can assert the VROUTPUT_ENABLE signal. After
VROUTPUT_ENABLE is asserted the sequence of powering up the VCCUNCORE,
VCCCORE and VCCCACHE supplies begins. The VCCUNCORE, VCCCORE and VCCCACHE
supplies power the remainder of the sysint, the cores and the large cache arrays,
respectively.
When all supplies are up and stable, Ararat asserts VRPWRGD which signals the
external environment that it can assert the PWRGOOD signal. PWRGOOD assertion
initiates the processor internal cold reset sequence.
external environment that it can assert the PWRGOOD signal. PWRGOOD assertion
initiates the processor internal cold reset sequence.
It is important to keep in mind that during platform initialization, the RESET_N pin to
any component in the platform can be removed ONLY after all other components have
had sufficient time to sample their respective reset pins. This is needed to prevent
unknown behavior that may result if any one system component comes out of reset
before other components have received the reset signal.
any component in the platform can be removed ONLY after all other components have
had sufficient time to sample their respective reset pins. This is needed to prevent
unknown behavior that may result if any one system component comes out of reset
before other components have received the reset signal.
With the exception of standby miscellaneous pins, all input pins, bi-directional pins, and
terminated output pins must not be allowed to exceed the processor's actual VCCIO
voltage prior to and during ramp up of the VCCIO supply.
terminated output pins must not be allowed to exceed the processor's actual VCCIO
voltage prior to and during ramp up of the VCCIO supply.
2.12
Preferred Power-down Voltage Sequence
It should be noted that when the processor is required to be physically removed from
its socket, power rails VCC33_SM and Vcc(12 V) must also be powered down before
removal of the processor.
its socket, power rails VCC33_SM and Vcc(12 V) must also be powered down before
removal of the processor.
2.13
Test Access Port (TAP) Connection
The recommended TAP connectivity is detailed in the Intel
®
Itanium
®
Processor 9300
Series Platform Debug Port Design Guide.
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