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Intel
D425
ユーザーズマニュアル
Intel D425 AU80610006252AA ユーザーズマニュアル
製品コード
AU80610006252AA
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Datasheet
5
1.9.2
DID - Device Identification ...................................................... 105
1.9.3
PCICMD2 - PCI Command ....................................................... 106
1.9.4
PCISTS2 - PCI Status ............................................................. 107
1.9.5
RID2 - Revision Identification .................................................. 108
1.9.6
CC - Class Code .................................................................... 109
1.9.7
CLS - Cache Line Size ............................................................ 109
1.9.8
MLT2 - Master Latency Timer .................................................. 110
1.9.9
HDR2 - Header Type .............................................................. 110
1.9.10
MMADR - Memory Mapped Range Address ................................ 110
1.9.11
IOBAR - I/O Base Address ...................................................... 111
1.9.12
GMADR - Graphics Memory Range Address ............................... 112
1.9.13
GTTADR - Graphics Translation Table Range Address .................. 113
1.9.14
SVID2 - Subsystem Vendor Identification.................................. 113
1.9.15
SID2 - Subsystem Identification .............................................. 114
1.9.16
ROMADR - Video BIOS ROM Base Address................................. 114
1.9.17
CAPPOINT - Capabilities Pointer ............................................... 115
1.9.18
INTRLINE - Interrupt Line ....................................................... 115
1.9.19
INTRPIN - Interrupt Pin .......................................................... 116
1.9.20
MINGNT - Minimum Grant ...................................................... 116
1.9.21
MAXLAT - Maximum Latency ................................................... 116
1.9.22
CAPID0 - Mirror of Device 0 Capability Identifier ........................ 117
1.9.23
MGGC - GMCH Graphics Control Register .................................. 118
1.9.24
DEVEN - Device Enable .......................................................... 120
1.9.25
SSRW - Software Scratch Read Write ....................................... 121
1.9.26
BSM - Base of Stolen Memory ................................................. 121
1.9.27
HSRW - Hardware Scratch Read Write ...................................... 122
1.9.28
MSAC - Multi Size Aperture Control .......................................... 122
1.9.29
SCWBFC - Secondary CWB Flush Control .................................. 123
1.9.30
MSI_CAPID - Message Signaled Interrupts Capability ID ............. 123
1.9.31
MC - Message Control ............................................................ 124
1.9.32
MA - Message Address ........................................................... 125
1.9.33
MD - Message Data ............................................................... 125
1.9.34
GDRST - Graphics Debug Reset .............................................. 126
1.9.35
PMCAPID - Power Management Capabilities ID ........................... 127
1.9.36
PMCAP - Power Management Capabilities .................................. 127
1.9.37
PMCS - Power Management Control/Status ............................... 128
1.9.38
SWSMI - Software SMI ........................................................... 129
1.9.39
LBB - LBB-Legacy Backlight Brightness ..................................... 130
1.10
PCI Device 2 Function 1 ...................................................................... 130
1.10.1
VID2 - Vendor Identification ................................................... 132
1.10.2
DID2 - Device Identification .................................................... 133
1.10.3
PCICMD2 - PCI Command ....................................................... 133
1.10.4
PCISTS2 - PCI Status ............................................................. 135
1.10.5
RID2 - Revision Identification .................................................. 136
1.10.6
CC - Class Code Register ........................................................ 137
1.10.7
CLS - Cache Line Size ............................................................ 137
1.10.8
MLT2 - Master Latency Timer .................................................. 138
1.10.9
HDR2 - Header Type .............................................................. 138
1.10.10
MMADR - Memory Mapped Range Address ................................ 139
1.10.11
SVID2 - Subsystem Vendor Identification.................................. 139
1.10.12
SID2 - Subsystem Identification .............................................. 140
1.10.13
ROMADR - Video BIOS ROM Base Address................................. 140
1.10.14
CAPPOINT - Capabilities Pointer ............................................... 141
1.10.15
MINGNT - Minimum Grant ...................................................... 141
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