Intel Xeon L3406 CM80616005010AA ユーザーズマニュアル
製品コード
CM80616005010AA
Datasheet, Volume 2
131
Processor Integrated I/O (IIO) Configuration Registers
3.4.5.14
IR[4:7]—Increment Registers 4-7
3.4.5.15
IR[8:11]—Increment Registers 8-11
3.4.5.16
IR[12:15]—Increment Registers 12-15
Register:
IR[4:7]
Device:
8
Function:
1
Offset:
150h-15Ch by 4
Bit
Attr
Default
Description
31:0
RWSLB
0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.
Register:
IR[8:11]
Device:
8
Function:
1
Offset:
160h-16Ch by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.
Register:
IR[12:15]
Device:
8
Function:
1
Offset:
170h-17Ch by 4
Bit
Attr
Default
Description
31:0
RWLB
0h
Increment
These registers are physically mapped to scratch pad registers. A read from IR[n]
These registers are physically mapped to scratch pad registers. A read from IR[n]
reads SR[n] and then increments SR[n]. A write to IR[n] increments SR[n] while
the write data is unused. Increments within SR[n] for reads and writes roll over to
zero. The read or write and the increment side effect are atomic with respect to
other accesses. The registers provide firmware with synchronization variables
(semaphores) that are overloaded onto the same physical registers as SR.