Intel Xeon L3406 CM80616005010AA ユーザーズマニュアル
製品コード
CM80616005010AA
Datasheet, Volume 2
219
Processor Uncore Configuration Registers
5:4
RWST
0
LLR_TO_LINK_RESET
Consecutive LLRs to Link Reset — Sticky, Late action.
00 = up to 16
01 = up to 8
10 = up to 4
11 = 0, disable LLR (if CRC error, immediate error condition).
Consecutive LLRs to Link Reset — Sticky, Late action.
00 = up to 16
01 = up to 8
10 = up to 4
11 = 0, disable LLR (if CRC error, immediate error condition).
3:2
RWST
0
LINK_RESET_FROM_LLR
Consecutive Link Reset from LLR till error condition (only applies if LLR enabled)
Consecutive Link Reset from LLR till error condition (only applies if LLR enabled)
— Sticky, Late action.
00 = up to 2
01 = up to 1
10 = up to 0
11 = Reserved.
00 = up to 2
01 = up to 1
10 = up to 0
11 = Reserved.
1
RW
0
LINK_HARD_RESET. Link Hard Reset
Re-initialize resetting values in sticky registers. Write 1 to reset this link. This is
Re-initialize resetting values in sticky registers. Write 1 to reset this link. This is
a destructive reset. When reset asserts, register clears to 0h.
0
RW
0
LINK_SOFT_RESET. Link Soft Reset
Re-initialize without resetting sticky registers. Write 1 to reset this link. This is a
Re-initialize without resetting sticky registers. Write 1 to reset this link. This is a
destructive reset. When reset asserts, register clears to 0h.
Device:
2
Function:
0
Offset:
48h
Access as a DWord
Bit
Type
Default
Description