Intel AT80604004884AA ユーザーズマニュアル
Intel® Xeon® Processor 7500 Datasheet, Volume 1
107
Signal Definitions
5
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 1 of 6)
Name
Type
Description
BOOTMODE[1:0]
I
The BOOTMODE[1:0] inputs are to specify which mode the Intel® Xeon® processor
7500 series will boot to. For details on the modes refer to the Intel® Xeon®
Processor 7500 Series Datasheet, Volume 2.
CVID[7:1]
O
Voltage ID driven out to the VR 11.1 for dynamic/static adjustment of processor
voltage set point. See VCACHE below. This signal has on die termination.
ERROR[0]_N
IO
Pulsed Signal. As output, signals un-corrected error condition of the processor. As an
input, can be programmed to signal Intel® Scalable Memory Interconnect to the
cores. Open drain
ERROR[1]_N
IO
Level Signal. As output, signals fatal error condition of the processor. As an input,
can be programmed to signal Intel® Scalable Memory Interconnect to the cores.
Open drain.
FBD0NBI[A/B][P/N][13:0]
I
These differential pair data signals generated from the branch zero, channel A and B
of Intel® Scalable Memory Interconnects are input to the Intel® Xeon® processor
7500 series.
Example: FBD0NBIAP[0] Intel® Scalable Memory Interconnect branch 0, North
bound data input lane 0 signal of channel A and positive bit of the differential pair.
FBD0NBICLK[A/B][P/N]0 I
These
differential pair clock signals generated from the branch zero, channel A and B
of Intel® Scalable Memory Interconnects are input to the Intel® Xeon® processor
7500 series.
Example: FBD0NBICLKAP0 Intel® Scalable Memory Interconnect branch 0,
Northbound clock input signal of channel A and positive bit of the differential pair.
FBD0SBO[A/B][P/N][10:0]
O
These differential pair output data signals generated from Intel® Xeon® processor
7500 series to the branch zero, channel A and B of Intel® Scalable Memory
Interconnects.
Example: FBD0SBOAP[0] Intel® Scalable Memory Interconnect branch 1,
southbound data output lane 0 signal of channel A and positive bit of the differential
pair.
Intel®
SMI
0
NB
I
A/B
P/N
[13:0]
Interface
Name
Branch
Number
North
Bound
Input
Channel
Differential
Pair
Polarity
Polarity
Positive/
Negative
Lane
Number
Intel®
SMI
0
NB
I
CLK
A/B
P/N
Interface
Name
Branch
Number
North
Bound
Input
Clock
Channel
Differential
Pair
Polarity
Polarity
Positive/
Negative
Intel®
SMI
0
SB
O
A/B
P/N
[10:0]
Interface
Name
Branch
Number
South
Bound
Output
Channel
Differential
Pair
Polarity
Polarity
Positive/
Negative
Lane
Number