Intel E3-1275 CM8062307262003 ユーザーズマニュアル
製品コード
CM8062307262003
Datasheet, Volume 1
83
Electrical Specifications
such that two processors at the same frequency may have different settings within the VID range. Note
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
that this differs from the VID employed by the processor during a power management event (Adaptive
Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).
3.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the
socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
socket with a 20-MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-M minimum
impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external
noise from the system is not coupled into the oscilloscope probe.
4.
ICC_MAX specification is based on the V
CC
loadline at worst case (highest) tolerance and ripple.
5.
The V
CC
specifications represent static and transient limits.
6.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE lands. Voltage
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
regulation feedback for voltage regulator circuits must also be taken from processor VCC_SENSE and
VSS_SENSE lands.
7.
PSx refers to the voltage regulator power state as set by the SVID protocol.
Notes:
1.
1.
Unless otherwise noted, all specifications in this table are based on estimates and simulations or empirical
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
data. These specifications will be updated with characterized data from silicon measurements at a later
date.
2.
V
CCSA
must be provided using a separate voltage source and not be connected to V
CC
. This specification is
measured at VCCSA_SENSE.
3.
±5% total. Minimum of ±2% DC and 3% AC at the sense point. di/dt = 50 A/us with 150 ns step.
Table 7-6.
Processor System Agent I/O Buffer Supply DC Voltage and Current
Specifications
Specifications
Symbol
Parameter
Min
Typ
Max
Unit
Note
1
V
CCSA
Voltage for the system agent
0.879
0.925
0.971
V
2
V
DDQ
Processor I/O supply voltage for
DDR3
DDR3
1.425
1.5
1.575
V
V
CCPLL
PLL supply voltage (DC + AC
specification)
specification)
1.71
1.8
1.89
V
V
CCIO
Processor I/O supply voltage for
other than DDR3
other than DDR3
-2/-3%
1.05
+2/+3%
V
3
I
SA
Current for the system agent
8.8
A
I
SA_TDC
Sustained current for the system
agent
agent
8.2
A
I
DDQ
Processor I/O supply current for
DDR3
DDR3
4.75
A
I
DDQ_TDC
Processor I/O supply sustained
current for DDR3
current for DDR3
4.75
A
I
DDQ_STANDBY
Processor I/O supply standby
current for DDR3
current for DDR3
1
A
I
CC_VCCPLL
PLL supply current
1.5
A
I
CC_VCCPLL_TDC
PLL sustained supply current
0.93
A
I
CC_VCCIO
Processor I/O supply current
8.5
A
I
CC_VCCIO_TDC
Processor I/O supply sustained
current
current
8.5
A