ASUS tr-dlsr ユーザーズマニュアル

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ASUS TR-DLSR User’s Manual
2.  FEATURES
Specifications
2.  FEA
TURES
2.1 ASUS TR-DLSR Motherboard
The ASUS TR-DLSR motherboard is designed primarily for multi-server
environments to optimize available space without sacrificing performance. Powered
by dual Intel
®
 Pentium
®
 III Tualatin™ processors, the TR-DLSR efficiently complies
with today’s  demand for a high-integration server.
2.1.1 Specifications
Latest Intel Processor Support: Supports dual Socket 370-based Intel Pentium
III Tualatin processors running up to 1.4GHz with 133MHz Front Side Bus (FSB)
frequency
Multi-Processor OS: Supports multi-processor operating systems such as
Windows NT/2000, Unix, Linux, and Netware when dual processors of the same
type and speed are installed.
ServerWorks LE 3.0 Chipset: Features the ServerWorks LE 3.0 North Bridge
and RCC Open South Bridge. Supports PC133 SDRAM with ECC, dual peer to
peer PCI buses, and 64-bit 66MHz PCI bus speed.
Onboard Graphics: Features ATI RAGE-XL PCI VGA controller that supports
up to 4MB PC100-compliant 10ns SDRAM for 1280x1024 and true color
resolutions.
Smart Networking: Features two Intel 82559 Fast-Ethernet LAN controllers
that fully support Alert-On-LAN II (AOL-II) and 10BASE-T/100BASE-TX.
PC133 Memory Support: Equipped with four Dual Inline Memory Module
(DIMM) sockets that support up to 4GB of registered ECC SDRAMs (available
in 64, 128, 256, 512MB, or 1GB  densities).
SCSI Support: Equipped with the LSI 53C1010 Ultra160 64-bit dual-channel
SCSI controller supports up to 30 SCSI devices.
Standard IDE Support: Comes with an onboard PCI Bus Master IDE controller
with two connectors that support four IDE devices on two channels. Supports
PIO Modes 3 and 4 IDE devices, such as DVD-ROM, CD-ROM, CD-R/RW,
LS-120, and Tape Backup drives.
PCI Expansion Slot: One 64-bit 66MHz PCI slot
USB Ports: Two stacked USB connectors to provide for additional peripherals
SMBus: Features the System Management Bus interface, which is used to
physically transport commands and information between SMBus devices.