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CCS Technical Documentation
Troubleshooting - Baseband
RH-27
Issue 1 11/2003      Confidential         ©
2003 Nokia Corporation
Page 13
CBUSClk Interface
A 1.2 MHz clock signal is used for CBUS, which is used by the MCU to transfer data 
between UEM and UPP.
DBUS Clk Interface
A 9.6 MHz clock signal is used for DBUS, which is used by the DSP to transfer data 
between UEM and UPP.
The system clock can stopped during sleep mode by disabling the VCTCXO power supply 
from the UEM regulator output (VR3) by turning off the controlled output signal SleepX 
from UPP.