Intel 41210 ユーザーズマニュアル
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
115
Register Description
12.2.61
Offset 134h: PCIXERRUNC_SEV—Uncorrectable
PCI-X Error Severity Register
PCI-X Error Severity Register
This register controls the severity of the reporting of PCI-X uncorrectable errors. There is one
mask bit per error. When a bit is set to 1, the corresponding error, when enabled, generates an
ERR_FATAL message on PCI Express*. When a bit is cleared to 0, the corresponding error,
when enabled, causes a ERR_NONFATAL on PCI Express*.
mask bit per error. When a bit is set to 1, the corresponding error, when enabled, generates an
ERR_FATAL message on PCI Express*. When a bit is cleared to 0, the corresponding error,
when enabled, causes a ERR_NONFATAL on PCI Express*.
Table 95.
Offset 130h: PCIXERRUNC_SEV—Uncorrectable PCI-X Error Severity Register
(Sheet 1 of 2)
(Sheet 1 of 2)
Bits
Type
Reset
Description
15:14
RsvdP
00b
Preserved
13
RWCS
0b
Internal Bridge Data Error Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
12
RWCS
0b
PCI-X SERR# Detected Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
11
RWCS
0b
PCI-X PERR# Detected Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
10
RWCS
0b
PCI Delayed Transaction Timer Expiry Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
9
RWCS
0b
PCI-X Uncorrectable Address Parity Error Detected Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
8
RWCS
0b
PCI-X Uncorrectable Attribute Parity Error Detected Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
7
RWCS
0b
PCI-X Uncorrectable Data Parity Error Detected Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
6
RWS
1b
Split Completion Message Data Error Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
5
RWS
0b
Unexpected Split Completion Error Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL
4
RsvdP
0b
Preserved
3
RWCS
0b
PCI-X Detected Master Abort Severity:
0 = ERR_NONFATAL
1 = ERR_FATAL