Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-10
Freescale Semiconductor
Interrupt Controller
7.2.4.6
ICTL Critical Priority and Main Interrupt Mask Register—MBAR + 0x0514
—
EENA[x]
Individual enable bits for each IRQ input pin. Setting the associated bit lets the related IRQ
pin generate interrupts. In either case, status indications in PSa and CSa (ICTL Peripheral
Interrupt Status All Register) are active.
pin generate interrupts. In either case, status indications in PSa and CSa (ICTL Peripheral
Interrupt Status All Register) are active.
20
EENA0
IRQ[0]
21
EENA1
IRQ[1]
22
EENA2
IRQ[2]
23
EENA3
IRQ[3]
24:30
—
Reserved
31
CEb
Critical Enable—a special control bit, which if set, directs critical interrupt sources to the
normal e300 core Interrupt pin. This is for system programmer who prefers to handle all
interrupts in a single ISR.
normal e300 core Interrupt pin. This is for system programmer who prefers to handle all
interrupts in a single ISR.
The status operation remains unchanged, it is necessary to parse Critical Status information
prior to Normal Status information to detect critical interrupt sources routed to the normal
interrupt pin.
prior to Normal Status information to detect critical interrupt sources routed to the normal
interrupt pin.
Table 7-9. ICTL Critical Priority and Main Interrupt Mask Register)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Crit0_pri
Crit1_pri
Crit2_pri
Crit3_pri
Reserved
Main_
Mask
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Main_Mask
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:1
Crit0_pri
Priority encoding value for Critical Interrupt 0, IRQ[0] input pin.
There are four Critical Interrupt sources that can be uniquely prioritized (a higher Priority
value creates a higher priority, i.e. a value of 3 is the highest priority value). In the case of
identical priority value, the lower numbered interrupt source has priority. This makes
IRQ[0] the highest default priority (being the lowest numbered source).
There are four Critical Interrupt sources that can be uniquely prioritized (a higher Priority
value creates a higher priority, i.e. a value of 3 is the highest priority value). In the case of
identical priority value, the lower numbered interrupt source has priority. This makes
IRQ[0] the highest default priority (being the lowest numbered source).
2:3
Crit1_pri
Priority encoding value for Slice Timer 0 interrupt source. Hard-wired as critical interrupt
source number 1, it has the second highest default priority.
source number 1, it has the second highest default priority.
4:5
Crit2_pri
Priority encoding value for HI_int interrupt source. Hard-wired as critical interrupt source
number 2. It is programmable such that any peripheral source can be directed to it, and
thus get maximum priority service.
number 2. It is programmable such that any peripheral source can be directed to it, and
thus get maximum priority service.
6:7
Crit3_pri
Priority encoding value for CCS WakeUp source. Hard-wired as critical interrupt source
number 3.
number 3.
8:14
—
Reserved
Bits
Name
Description