Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
7-34
Freescale Semiconductor
General Purpose I/O (GPIO)
7.3.2.1.4
GPS Simple GPIO Data Direction Register—MBAR + 0x0B0C
12:15
USB
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 12 controls GPIO_USB_3 (USB1_8 pin)
bit 13 controls GPIO_USB_2 (USB1_7 pin)
bit 14 controls GPIO_USB_1 (USB1_6 pin)
bit 15 controls GPIO_USB_0 (USB1_0 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
16:17
—
Reserved
18:23
PSC3
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 18 controls GPIO_ PSC3_5 (PSC3_7 pin)
bit 19 controls GPIO_ PSC3_4 (PSC3_6 pin)
bit 20 controls GPIO_ PSC3_3 (PSC3_3 pin)
bit 21 controls GPIO_ PSC3_2 (PSC3_2 pin)
bit 22 controls GPIO_ PSC3_1 (PSC3_1 pin)
bit 23 controls GPIO_ PSC3_0 (PSC3_0 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
24:27
PSC2
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 24 controls GPIO_PSC2_3 (PSC2_3 pin)
bit 25 controls GPIO_PSC2_2 (PSC2_2 pin)
bit 26 controls GPIO_PSC2_1 (PSC2_1 pin)
bit 27 controls GPIO_PSC2_0 (PSC2_0 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
28:31
PSC1
Individual bits to cause open drain emulation for pins configured as GPIO output.
bit 28 controls GPIO_PSC1_3 (PSC1_3 pin)
bit 29 controls GPIO_PSC1_2 (PSC1_2 pin)
bit 30 controls GPIO_PSC1_1 (PSC1_1 pin)
bit 31 controls GPIO_PSC1_0 (PSC1_0 pin)
0 = Normal CMOS output (default)
1 = Open Drain emulation (a drive to high creates Hi-Z)
Table 7-24. GPS Simple GPIO Data Direction Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
IRDA
ETHR
Reserved
USB
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
PSC3
PSC2
PSC1
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description