Freescale Semiconductor MPC5200B ユーザーズマニュアル
General Purpose I/O (GPIO)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-39
7.3.2.1.7
GPS GPIO Output-Only Enables Register —MBAR + 0x0B18
12:15
USB
Individual status bits reflecting the state of corresponding GPIO pins.
bit 12 reflects GPIO_USB_3 (USB1_8 pin)
bit 13 reflects GPIO_USB_2 (USB1_7 pin)
bit 14 reflects GPIO_USB_1 (USB1_6 pin)
bit 15 reflects GPIO_USB_0 (USB1_0 pin)
16:17
—
Reserved
18:23
PSC3
Individual status bits reflecting the state of corresponding GPIO pins.
bit 18 reflects GPIO_ PSC3_5 (PSC3_7 pin)
bit 19 reflects GPIO_ PSC3_4 (PSC3_6 pin)
bit 20 reflects GPIO_ PSC3_3 (PSC3_3 pin)
bit 21 reflects GPIO_ PSC3_2 (PSC3_2 pin)
bit 22 reflects GPIO_ PSC3_1 (PSC3_1 pin)
bit 23 reflects GPIO_ PSC3_0 (PSC3_0 pin)
24:27
PSC2
Individual status bits reflecting the state of corresponding GPIO pins.
bit 24 reflects GPIO_PSC2_3 (PSC2_3 pin)
bit 25 reflects GPIO_PSC2_2 (PSC2_2 pin)
bit 26 reflects GPIO_PSC2_1 (PSC2_1 pin)
bit 27 reflects GPIO_PSC2_0 (PSC2_0 pin)
28:31
PSC1
Individual status bits reflecting the state of corresponding GPIO pins.
bit 28 reflects GPIO_PSC1_3 (PSC1_3 pin)
bit 29 reflects GPIO_PSC1_2 (PSC1_2 pin)
bit 30 reflects GPIO_PSC1_1 (PSC1_1 pin)
bit 31 reflects GPIO_PSC1_0 (PSC1_0 pin)
Note: These status bits operate regardless of the function on the pin.
Table 7-27. GPS GPIO Output-Only Enables Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
ETHR
Reserved
I2C
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description