Freescale Semiconductor MPC5200B ユーザーズマニュアル
General Purpose Timers (GPT)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
7-55
7.4
General Purpose Timers (GPT)
Eight (8) General-Purpose Timer (GPT) pins are configurable for:
•
Input Capture
•
Output Compare
•
Pulse Width Modulation (PWM) Output
•
Simple GPIO
•
Internal CPU timer
•
Watchdog Timer (on GPT0 only)
Timer modules run off the internal IP bus clock. Each Timer is associated to a single I/O pin. Each Timer has a 16-bit prescaler and 16-bit
counter, thus achieving a 32-bit range (but only 16-bit resolution).
counter, thus achieving a 32-bit range (but only 16-bit resolution).
7.4.1
Timer Configuration Method
Use the following method to configure each timer:
1.
Determine the Mode Select field (Timer_MS) value for the desired operation.
2.
Program any other registers associated with this mode.
3.
Program Interrupt enable as desired.
4.
Enable the Timer by writing the Mode Select value into the Timer_MS field.
7.4.2
Mode Overview
The following gives a brief description of the available modes:
1.
Input Capture—In this mode the I/O pin is an Input. Once enabled, the counters run until the specified “Capture Event” occurs
(rise, fall, either, or pulse). At the Capture Event, the counter value is latched in the status register. If enabled, a CPU interrupt is
generated. The GP Timers 6 & 7 are active during low power modes (except for deep sleep), and therefore have the ability to initiate
a wake up the device from a low-power mode.
(rise, fall, either, or pulse). At the Capture Event, the counter value is latched in the status register. If enabled, a CPU interrupt is
generated. The GP Timers 6 & 7 are active during low power modes (except for deep sleep), and therefore have the ability to initiate
a wake up the device from a low-power mode.
2.
Output Compare—In this mode the I/O pin is an Output. When enabled the counters run until they reach the programmed
Terminal Count value. At this point, the specified “Output Event” is generated (toggle, pulse hi, or pulse low). If enabled, a CPU
interrupt is generated.
Terminal Count value. At this point, the specified “Output Event” is generated (toggle, pulse hi, or pulse low). If enabled, a CPU
interrupt is generated.
3.
PWM—In this mode the I/O pin is an Output. The user can program “Period” and “Width” values to create an adjustable,
repeating output waveform on the I/O pin. A CPU interrupt can be generated at the beginning of each PWM Period, at which time
a new Width value can be loaded. The new Width value, which represents “ON time”, is automatically applied at the beginning of
the next period. Note that there is no interrupt at the beginning of the first PWM Period. This mode is suitable for PWM audio
encoding.
repeating output waveform on the I/O pin. A CPU interrupt can be generated at the beginning of each PWM Period, at which time
a new Width value can be loaded. The new Width value, which represents “ON time”, is automatically applied at the beginning of
the next period. Note that there is no interrupt at the beginning of the first PWM Period. This mode is suitable for PWM audio
encoding.
4.
Simple GPIO—In this mode the I/O pin operates as a GPIO pin. It can be specified as Input or Output, according to the
programmable GPIO field. GPIO mode is mutually exclusive of modes
programmable GPIO field. GPIO mode is mutually exclusive of modes
1
through
3
(listed above). In GPIO mode, modes
5
through
6
(listed below) remain available.
5.
CPU Timer—The I/O pin is not used in this mode. Once enabled, the counters run until they reach a programmed Terminal
Count. When this occurs, an interrupt can be generated to the CPU. This Timer mode can be used simultaneously with the Simple
GPIO mode.
Count. When this occurs, an interrupt can be generated to the CPU. This Timer mode can be used simultaneously with the Simple
GPIO mode.
6.
Watchdog Timer—This is a special CPU Timer mode, available only on Timer 0. The user must enable the Watchdog Timer
mode, which is not active upon reset. The Terminal Count value is programmable. If the counter is allowed to expire, a full
MPC5200B reset occurs. To prevent the Watchdog Timer from expiring, software must periodically write a specific value to a
specific register (in Timer 0). This causes the counter to reset.
mode, which is not active upon reset. The Terminal Count value is programmable. If the counter is allowed to expire, a full
MPC5200B reset occurs. To prevent the Watchdog Timer from expiring, software must periodically write a specific value to a
specific register (in Timer 0). This causes the counter to reset.
7.4.3
Programming Notes
Programmers should observe the following notes:
1.
Intermediate values of the Timer internal counters are not readable by software.
2.
The Stop_Cont bit operates differently for different modes. In general, this bit controls whether the Timer halts at the end of a
current mode, or resets and continues with a repetition of the mode. See the Bit Description for precise operation.
current mode, or resets and continues with a repetition of the mode. See the Bit Description for precise operation.
3.
The Timer_MS field operates somewhat as a Global Enable. If it is zero, then all Timer modes are disabled and internal counters
are reset. See the Bit Descriptions for more detail.
are reset. See the Bit Descriptions for more detail.
4.
There is a CE (Counter Enable) bit that operates somewhat independently of the Timer_MS field. This bit controls the Counter for
CPU Timer or Watchdog Timer modes only. See the Bit Descriptions to understand the operation of these bits across the various
modes.
CPU Timer or Watchdog Timer modes only. See the Bit Descriptions to understand the operation of these bits across the various
modes.