Freescale Semiconductor MPC5200B ユーザーズマニュアル

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Memory Controller Registers (MBAR+0x0100:0x010C)
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
8-25
8.7.3
Configuration Register 1—MBAR + 0x0108
The 32-bit read/write Configuration register 1 stores delay values necessary between specific SDRAM commands. During initialization, 
software loads values to the register according to the SDRAM information obtained from the data sheet. This register is reset only by a 
power-up reset signal.
The Read and Write Latency fields govern the relative timing of commands and data, and must be exact values. All other fields govern the 
relative timing from one command to another, they have minimum values but any larger value is also legal (but with decreased performance). 
The “suggested values” are based on the maximum routing delay of memory signals and the MPC5200B maximum memory frequency of 
133MHz; they do not guarantee maximum performance for actual board routing delay or operating frequency.
The minimum values of certain fields can be different for SDR and DDR SDRAM, even if the data sheet timing is the same, because:
In SDR mode, the Memory Controller counts the delay in MEM_CLK
In DDR mode, the Memory Controller counts the delay in 2xMEM_CLK (also referred to as MEM_CLK2)
MEM_CLK—Memory Controller clock—is the speed of the SDRAM interface and is equal to the internal XL bus clock. 
MEM_CLK is fixed at boot time along with the XL bus clock, via the HW RESET WORD setting. It is an integer multiple of the 
external reference clock (e.g., 66MHz, 99MHz or 132MHz if a 33MHz reference is used).
Table 8-9. 16-Bit SDRAM Address Multiplexing
Device
Structure
Row bits 
×
Col bits 
×
Bank bits
hi_
addr
Internal XLA[4:30]
4
5
6
7
8
9:19
20:21
22:30
64Mbit
8Mx8bit
12x9x2
0
a
a
All MEM_MA pins are driven in all cases, but only the bits used by memory are listed.
RA[11:0]
BA
[1:0]
CA
[8:0]
128Mbit
8Mx16bit
12x9x2
0
RA[11:0]
BA
[1:0]
CA
[8:0]
16Mx8bit
12x10x2
0
CA9
13x9x2
1
RA12
256Mbit
8Mx32bit
12x9x2
0
RA[11:0]
BA
[1:0]
CA
[8:0]
16Mx16bit
12x10x2
0
CA9
13x9x2
1
RA12
32Mx8bit
12x11x2
0
CA11
CA9
13x10x2
1
CA9
RA12
512Mbit
16Mx32bit
12x10x2
0
CA9
RA[11:0]
BA
[1:0]
CA
[8:0]
13x9x2
1
RA12
32Mx16bit
12x11x2
0
CA11
CA9
13x10x2
1
CA9
RA12
64Mx8bit
12x12x2
0
CA12 CA11
CA9
13x11x2
1
CA11
CA9
RA12
1Gbit
32Mx32bit
12x11x2
0
CA11
CA9
RA[11:0]
BA
[1:0]
CA
[8:0]
13x10x2
1
CA9
RA12
64Mx16bit
12x12x2
0
CA12 CA11
CA9
13x11x2
1
CA11
CA9
RA12
2Gbit
64Mx32bit
12x12x2
0
CA12 CA11
CA9
RA[11:0]
BA
[1:0]
CA
[8:0]
13x11x2
1
CA11
CA9
RA12