Freescale Semiconductor MPC5200B ユーザーズマニュアル
Programmer’s Model
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
9-17
9.7.1.3
Chip Select Control Register—MBAR + 0x0318
28
WS
Write Swap bit—If high, Endian byte swapping occurs during writes to a peripheral.
•
For 8-bit peripherals, this bit has no effect.
•
For 16-bit peripherals, byte swapping can occur.
•
For 32-bit peripherals (possible in MUXed mode only) byte swap can occur.
1 = swap
0 = NO swap
2-byte swap is AB to BA, 4-byte swap is ABCD to DCBA.
Note: Transactions at less than the defined port size (i.e., data size) apply swap rules as
above, according to the current transaction size.
above, according to the current transaction size.
29
RS
Read Swap bit—Same as WS, but swapping is done when reading data from a peripheral.
1 = swap
0 = NO swap
Note: Transactions at less than the defined port size (i.e., data size) apply swap rules as
above, according to the current transaction size.
above, according to the current transaction size.
30
WO
Write Only bit—If high peripheral is treated as a write-only device. An attempted Read
access results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or
an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction
is presented to the peripheral.
access results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or
an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction
is presented to the peripheral.
A bus error means the internal cycle is terminated with a transfer error acknowledge
(ips_xfr_err assertion to IP bus, TEA assertion to XL bus).
(ips_xfr_err assertion to IP bus, TEA assertion to XL bus).
31
RO
Read Only bit—If high, peripheral is treated as a read-only device. An attempted Write
access results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or
an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction
is presented to the peripheral.
access results in a bus error (as specified by Chip Select Control Register EBEE bit) and/or
an interrupt (as dictated by Chip Select Control Register IE bit). In any case, no transaction
is presented to the peripheral.
Note:
1.
Large Flash mode is used, if AS is set to 11 and DS is set to 00 or 01.
2.
MOST Graphics mode is used, if AS is set to 10 and DS is set to 11.
Table 9-9. Chip Select Control Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
ME
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description