Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-10
Freescale Semiconductor
Registers
10.3.1.3
Revision ID/ Class Code Registers PCICCRIR(R) —MBAR + 0x0D08
10.3.1.4
Configuration 1 Register PCICR1(R/RW) —MBAR + 0x0D0C
30
Memory
Access
Control
Control
(M)
This bit controls the PCI controller’s response to Memory Space accesses. A value of 0
disables the response. A value of 1 allows the controller to recognize a Memory access.
disables the response. A value of 1 allows the controller to recognize a Memory access.
This bit is programmable (read/write from both the IP bus and PCI bus Configuration
cycles).
cycles).
31
IO access
Control
(IO)
Fixed to 0. This bit is not implemented because there is no MPC5200B IO type space
accessible from the PCI bus. The PCI base address registers are Memory address ranges
only. Initialization software should write a 0 to this bit location.
accessible from the PCI bus. The PCI base address registers are Memory address ranges
only. Initialization software should write a 0 to this bit location.
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Class Code
W
RESET
0x0680
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Class Code (continued)
Revision ID
W
RESET
0x00
0x00
Bits
Name
Description
0:23
Class Code
This field is read-only and represents the PCI Class Code assigned to MPC5200B
Its value is: 0x068000. (Other bridge device)
24:31
Revision ID
This field is read-only and represents the PCI Revision Id for this version of MPC5200B. Its
value is: 0x00.
value is: 0x00.
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
BIST
Header Type
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Lat timer[7:3]
Lat Timer[2:0]
Reserved
Cache Line Size
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description