Freescale Semiconductor MPC5200B ユーザーズマニュアル
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-13
10.3.1.10
Capabilities Pointer (Cap_Ptr) PCICPR(R)—MBAR + 0x0D34
Not implemented. Fixed to 0x00000000.
10.3.1.11
Configuration 2 Register PCICR2 (R/RW) —MBAR + 0x0D3C
10.3.2
General Control/Status Registers
The General Control/Status Registers primarily address the configurability of the XL bus Initiator and Target Interfaces, though some also
address global options which affect the Multi-Channel DMA interface (BestComm). These registers are accessed primarily internally as
offsets of MBAR, but can also be accessed by an external PCI master if PCI base and Target base address registers are configured to access
the space. See
address global options which affect the Multi-Channel DMA interface (BestComm). These registers are accessed primarily internally as
offsets of MBAR, but can also be accessed by an external PCI master if PCI base and Target base address registers are configured to access
the space. See
on configuring address windows.
10.3.2.1
Global Status/Control Register PCIGSCR(RW) —MBAR + 0x0D60
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Maximum Latency
Minimum Grant
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Interrupt Pin
Interrupt Line
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:7
Maximum
Latency
(Max_Lat)
Specifies how often, in units of 1/4 microseconds, the PCI controller would like to have
access to the PCI bus as master. A value of zero indicates the device has no stringent
requirement in this area. The register is read/write to/from the Slave bus, but read only from
the PCI bus.
access to the PCI bus as master. A value of zero indicates the device has no stringent
requirement in this area. The register is read/write to/from the Slave bus, but read only from
the PCI bus.
Note: The MPC5200B does NOT support initiator latency time-outs, the internal PCI Arbiter
does not support preemption of the internal masters XIPCI or SCPCI. The internal master
is granted until the transaction has been completed. The Latency Timer (LT) cannot
terminate any transfer.
does not support preemption of the internal masters XIPCI or SCPCI. The internal master
is granted until the transaction has been completed. The Latency Timer (LT) cannot
terminate any transfer.
8:15
Minimum Grant
(Min_Gnt)
The value programmed to this register indicates how long the PCI controller as master
would like to retain PCI bus ownership whenever it initiates a transaction. The register is
programmable from the Slave bus, but read only from the PCI bus.
would like to retain PCI bus ownership whenever it initiates a transaction. The register is
programmable from the Slave bus, but read only from the PCI bus.
16:23
Interrupt Pin
Fixed to 0x00. Indicates that this device does NOT use an interrupt request pin.
24:31
Interrupt Line
Fixed to 0x00. The Interrupt Line register stores a value that identifies which input on a PCI
interrupt controller the function’s PCI interrupt request pin. Since no interrupt request pin is
used, as specified in the Interrupt Pin register, this register has no function.
interrupt controller the function’s PCI interrupt request pin. Since no interrupt request pin is
used, as specified in the Interrupt Pin register, this register has no function.
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Rsvd
BM
PE
SE
Rsvd
XL Bus_clk to
PCI_CLK differential
Reserved
ipg_clk to PCI_CLK
differential
W
rwc
rwc
rwc
RESET
0
0
0
0
0
x
x
x
0
0
0
0
0
x
x
x