Freescale Semiconductor MPC5200B ユーザーズマニュアル
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-17
10.3.2.4
Target Control Register PCITCR(RW) —MBAR + 0x0D6C
Bits
Name
Description
0:1
Base Address
Translation 1
This base address register corresponds to a hit on the BAR1 in MPC5200B PCI Type 0
Configuration space register (PCI space). When there is a hit on MPC5200B PCI BAR1
(MPC5200B as Target), the upper 2 bits of the external PCI address (1Gbyte boundary)
are written over by this register value to address some 1Gbyte space in MPC5200B. This
register can be reprogrammed to move the window of MPC5200B address space
accessed during a hit in PCIBAR1. It should be written by software during initialization to
point to the internal SDR/DDR memory space.
Configuration space register (PCI space). When there is a hit on MPC5200B PCI BAR1
(MPC5200B as Target), the upper 2 bits of the external PCI address (1Gbyte boundary)
are written over by this register value to address some 1Gbyte space in MPC5200B. This
register can be reprogrammed to move the window of MPC5200B address space
accessed during a hit in PCIBAR1. It should be written by software during initialization to
point to the internal SDR/DDR memory space.
Note: This register should not point to the LocalPlus Memory Space. This is not
supported.
supported.
2:30
Reserved
Unused bits. Software should write zero to this register.
31
Enable 1
This bit enables a transaction in BAR1 space. If this bit is zero and a hit on MPC5200B
PCI BAR1 occurs, the target interface gasket will abort the PCI transaction.
PCI BAR1 occurs, the target interface gasket will abort the PCI transaction.
msb
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
LD
Reserved
P
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
WC
D
Write Combine Timer [7:0]
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
Bits
Name
Description
0:6
Reserved
Unused bits. Software should write zero to this register.
7
Latrule
Disable
(LD)
This control bit applies only when MPC5200B is Target. When set, it prevents the PCI
Controller from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.
Controller from automatically issuing a retry disconnect due to the PCI 16/8 clock rule.
The bit must be set before the 15th PCI clock for the first transfer and before the 7th clock
for other transfers.
for other transfers.
8:14
Reserved
Unused bits. Software should write zero to this register.
15
Prefetch Reads
(P)
This bit controls fetching a line from memory in anticipation of a request from the external
master. The target interface will continue to prefetch lines from memory as long as
PCI_FRAME is asserted and there is space to store the data in the target read buffer.
master. The target interface will continue to prefetch lines from memory as long as
PCI_FRAME is asserted and there is space to store the data in the target read buffer.
Note: This bit only applies to PCI reads in the address range for BAR 1 (prefetchable
memory).
memory).
Note: Prefetching is performed in response to a PCI memory-read-multiple command even
if this bit is cleared.
if this bit is cleared.
16:22
Reserved
Unused bits. Software should write zero to this register.