Freescale Semiconductor MPC5200B ユーザーズマニュアル
Registers
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-23
10.3.2.12
Configuration Address Register PCICAR (RW) —MBAR + 0x0DF8
10.3.3
Communication Sub-System Interface Registers
The Communication Sub-System/Multi-Channel DMA interface (also shortly referred to as SCPCI) has separate control registers for transmit
and receive operations.
and receive operations.
10.3.3.1
Multi-Channel DMA Transmit Interface
PCI Tx is controlled by 14 ‘32-bit’ registers. These registers are located at an offset 0x3800 from MBAR. Register addresses are relative to
this offset.
this offset.
7
PCI Arbiter Soft
Reset (ASR)
This bit puts the PCI Arbiter in a reset condition.
1 = reset the PCI Arbiter
0 = release the PCI Arbiter
Note: Resetting the PCI arbiter will disrupt any related transaction in progress and should
be reserved only for error conditions, or when it is known that no PCI or AD bus transactions
are in progress.
be reserved only for error conditions, or when it is known that no PCI or AD bus transactions
are in progress.
8:31
Reserved
Unused bits. Software should write zero to this register.
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
E
Reserved
Bus Number
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Device Number
Function Number
dword
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
Enable
(E)
The enable flag that controls configuration space mapping. When enabled, subsequent
access to initiator window space defined as I/O in the PCIIWCR is translated into a PCI
configuration access using the Configuration Address Register information (
access to initiator window space defined as I/O in the PCIIWCR is translated into a PCI
configuration access using the Configuration Address Register information (
). When disabled, a read or write to the window is passed through to
the PCI bus as an I/O transaction using the.
1 = Enabled
0 = Disabled
1:7
Reserved
Unused bits. Software should write zero to this register.
8:15
Bus
Number
This register field is an encoded value used to select the target bus of the configuration
access. For target devices on the PCI bus connected to MPC5200B, this field should be set
to 0x00.
access. For target devices on the PCI bus connected to MPC5200B, this field should be set
to 0x00.
16:20
Device
Number
This field is used to select a specific device on the target bus.
21:23
Function
Number
This field is used to select a specific function in the requested device. Single-function
devices should respond to function number 0b000.
devices should respond to function number 0b000.
24:29
dword
This field is used to select the dword address offset in the configuration space of the target
device.
device.
30:31
Reserved
Unused bits. Software should write zero to this register.