Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-32
Freescale Semiconductor
Registers
10.3.3.1.12 Tx FIFO Control Register PCITFCR(RW) —MBAR + 0x3848
10.3.3.1.13 Tx FIFO Alarm Register PCITFAR(RW) —MBAR + 0x384C
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
GR
IP_MASK
F
AE_MAS
K
RXW_MASK
U
F
_MASK
O
F
_MASK
Reserved
W
RESET
0
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:4
Reserved
Unused. Software shall write zero to these bits. (R/W)
5:7
Granularity
(GR)
Granularity bits control high “watermark” point at which FIFO negates Alarm condition (i.e.,
request for data). It represents the number of free Bytes, which is given by the granularity
value multiplied by 4.
request for data). It represents the number of free Bytes, which is given by the granularity
value multiplied by 4.
Note: A granularity setting of zero should be avoided because it means the Alarm bit (and
the Requestor signal) will not negate until the FIFO is completely full. The Multi-Channel
DMA module may perform up to 2 additional data writes after the negation of a Requestor
due to its internal pipelining
the Requestor signal) will not negate until the FIFO is completely full. The Multi-Channel
DMA module may perform up to 2 additional data writes after the negation of a Requestor
due to its internal pipelining
Note: This field must be set to a value of 4 or higher. When the FIFO granularity is 0 - 3,
read data can be corrupted with no error indication when the PCI controller simultaneously
writes to the same location that the BestComm is reading from. The workaround is to use a
FIFO granularity of 4 or greater.
read data can be corrupted with no error indication when the PCI controller simultaneously
writes to the same location that the BestComm is reading from. The workaround is to use a
FIFO granularity of 4 or greater.
8
IP_MASK
Illegal Pointer Mask
When this bit is set, the FIFO controller masks the Status register’s IP bit from generating an
error.
error.
9
FAE_MASK
When this bit is set, the FIFO controller masks the Status Register’s FAE bit from generating
an error.
an error.
10
RXW_MASK
When this bit is set, the FIFO controller masks the Status Register’s RXW bit from generating
an error. (To help with backward compatibility, this bit is asserted at reset.)
an error. (To help with backward compatibility, this bit is asserted at reset.)
11
UF_MASK
When this bit is set, the FIFO controller masks the Status Register’s UF bit from generating
an error.
an error.
12
OF_MASK
When this bit is set, the FIFO controller masks the Status Register’s OF bit from generating
an error.
an error.
13:15
Reserved
Unused. Software should write zero to these bits.
16:31
Reserved
Unused. Software should write zero to these bits. (R/W)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0