Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
10-42
Freescale Semiconductor
Registers
10.3.3.2.12 Rx FIFO Control Register PCIRFCR(RW) —MBAR + 0x38C8
R
Reserved
RXW
UF
OF
FR
Full
Alarm
Empty
W
rwc
rwc
rwc
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:8
Reserved
Unused byte. Software should write zero to these bits.
9
Receive Wait
Condition
(RXW)
This flag bit indicates that the ipf_rcv bus is incurring wait states because there is not
enough room in the FIFO to accept the data without causing overflow. This bit will cause the
error outputs (fifoError, ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in
the FIFO Control register is set. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to its bit position.
enough room in the FIFO to accept the data without causing overflow. This bit will cause the
error outputs (fifoError, ipf_rcv_error, ipf_xmit_error) to assert unless the RXW_MASK bit in
the FIFO Control register is set. Resetting the FIFO will clear this condition and the flag bit
is cleared by writing a one to its bit position.
10
UnderFlow
(UF)
This flag bit indicates that the read pointer has surpassed the write pointer. In other words
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
the FIFO has been read beyond Empty. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
11
OverFlow
(OF)
This flag bit indicates that the write pointer has surpassed the read pointer. In other words
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
the FIFO has been written beyond Full. Resetting the FIFO will clear this condition and the
flag bit is cleared by writing a one to its bit position.
12
Frame Ready
(FR)
The FIFO has a complete Frame of data ready for transmission. This module
does not provide support for Data Framing applications, so this bit should be ignored.
13
Full
The FIFO is Full. This is not a sticky bit or error condition. The Full indication tracks with the
state of the FIFO.
state of the FIFO.
14
Alarm
When the FIFO pointer is at or above the Alarm “watermark”, as written by the user
according to the Alarm and Control registers settings, the Alarm bit is asserted, thus
automatically signalling to the DMA engine that the FIFO needs to be ‘emptied’. By writing
a ‘1’ to this location software can enforce re-evaluation of the alarm condition.
according to the Alarm and Control registers settings, the Alarm bit is asserted, thus
automatically signalling to the DMA engine that the FIFO needs to be ‘emptied’. By writing
a ‘1’ to this location software can enforce re-evaluation of the alarm condition.
15
Empty
The FIFO is empty. This is not a sticky bit or error condition.
16:31
Reserved
Unused. Software should write zero to these bits.
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
GR
IP_MAS
K
F
AE_MASK
RXW_MASK
UF_
M
A
S
K
OF_MASK
Reserved
W
RESET
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1