Freescale Semiconductor MPC5200B ユーザーズマニュアル
Functional Description
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
10-45
NOTE
Only the internal PCI arbiter of the MPC5200B can be used as PCI arbiter for the PCI bus. An external
PCI arbiter cannot be used.
PCI arbiter cannot be used.
The registers, described in
, control and provide information about these multiple interfaces. An additional
Configuration interface allows internal access through the Slave bus(also referred to as IP bus) to the PCI Type 0 Configuration registers,
which are accessible to both MPC5200B and external masters through the PCI bus.
which are accessible to both MPC5200B and external masters through the PCI bus.
The following sections describe the operation of the PCI module.
10.4.1
PCI Bus Protocol
This section will provide a simple overview of the PCI bus protocol, including some details of MPC5200B implementation. For details
regarding PCI bus operation, refer to the PCI Local Bus Specification, Revision 2.2.
regarding PCI bus operation, refer to the PCI Local Bus Specification, Revision 2.2.
10.4.1.1
PCI Bus Background
The PCI interface is synchronous and is best used for bursting data in large chunks. Its maximum theoretical bandwidth approaches 266
Megabytes per second for the 32-bit implementation running at 66MHz. A system will contain one device that is responsible for configuring
all other devices on the bus upon reset. Each device has 256 bytes of configuration space that define individual requirements to the system
controller. These registers are read and written through a “configuration access” command. A PCI transfer is started by the master and is
directed toward a specific target. A provision is made for broadcasting to several targets through the “special command.” Data is transferred
through the use of memory and IO read and write commands.
Megabytes per second for the 32-bit implementation running at 66MHz. A system will contain one device that is responsible for configuring
all other devices on the bus upon reset. Each device has 256 bytes of configuration space that define individual requirements to the system
controller. These registers are read and written through a “configuration access” command. A PCI transfer is started by the master and is
directed toward a specific target. A provision is made for broadcasting to several targets through the “special command.” Data is transferred
through the use of memory and IO read and write commands.
.
10.4.1.2
Basic Transfer Control
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one or more data phases.
Fundamentally, all PCI data transfers are controlled by three signals FRAME, IRDY, and TRDY. An initiator asserts FRAME to indicate the
beginning of a PCI bus transaction and negates FRAME to indicate the end of a PCI bus transaction. An initiator negates IRDY to force wait
cycles. A target negates TRDY to force wait cycles.
Fundamentally, all PCI data transfers are controlled by three signals FRAME, IRDY, and TRDY. An initiator asserts FRAME to indicate the
beginning of a PCI bus transaction and negates FRAME to indicate the end of a PCI bus transaction. An initiator negates IRDY to force wait
cycles. A target negates TRDY to force wait cycles.
The PCI bus is considered idle when both FRAME and IRDY are negated. The first clock cycle in which FRAME is asserted indicates the
beginning of the address phase. The address and bus command code are transferred in that first cycle. The next cycle begins the first of one
beginning of the address phase. The address and bus command code are transferred in that first cycle. The next cycle begins the first of one
Table 10-4. PCI Command encoding
C/BE[3:0]
Command Type
0000
Interrupt Acknowledge
0001
Special Cycle
0010
I/O Read
0011
I/O Write
0100
Reserved
0101
Reserved
0110
Memory Read
0111
Memory Write
1000
Reserved
1001
Reserved
1010
Configuration Read
1011
Configuration Write
1100
Memory Read Multiple
1101
Dual Address Cycle
1110
Memory Read Line
1111
Memory Write and Invalidate