Freescale Semiconductor MPC5200B ユーザーズマニュアル
ATA Register Interface
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
11-11
11.3.2.5
ATA Rx/Tx FIFO Read Pointer Register—MBAR + 0x3A4C
11.3.2.6
ATA Rx/Tx FIFO Write Pointer Register—MBAR + 0x3A50
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
Alarm
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:19
—
Reserved
20:31
Alarm
User writes these bits to set low level “watermark”, which is the point where FIFO asserts
request for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32,
alarm condition occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not
negate until high level mark is reached, as specified by FIFO control register granularity bits.
request for BestComm Controller data filling. Value is in bytes. For example, with Alarm = 32,
alarm condition occurs when FIFO contains 32Bytes or less. Once asserted, alarm does not
negate until high level mark is reached, as specified by FIFO control register granularity bits.
Table 11-17. ATA Rx/Tx FIFO Read Pointer Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
ReadPtr
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0:19
—
Reserved
20:31
ReadPtr
Value is maintained by FIFO hardware and is NOT normally written. It can be adjusted in
special cases, but this disrupts data flow integrity. Value represents the Read address
presented to the FIFO RAM.
special cases, but this disrupts data flow integrity. Value represents the Read address
presented to the FIFO RAM.
Table 11-18. ATA Rx/Tx FIFO Write Pointer Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
WritePtr
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0