Freescale Semiconductor MPC5200B ユーザーズマニュアル
ATA Register Interface
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
11-19
11.3.3.12
ATA Drive Device Status Register—MBAR + 0x3A7C
Table 11-30. ATA Drive Device Status Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
BSY
DRDY
Data
DRQ
Reserved
ERR
Rsvd
HUT
FR
FE
IE
UDMA
Read
Write
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
0
BSY
Indicates drive is busy processing a command.
1
DRDY
Indicates drive is ready to accept executable commands.
2:3
Data
Command dependent—Register is written only when ATA drive status register bits BSY and
DRQ equal 0 and DMACK is not asserted. If this register is written when BSY and DRQ bits
are set to 1, the result is indeterminate.
DRQ equal 0 and DMACK is not asserted. If this register is written when BSY and DRQ bits
are set to 1, the result is indeterminate.
Register content is not valid when drive is in sleep mode.
4
DRQ
Indicates drive is ready to transfer a data word.
5:6
—
Reserved
7
ERR
Set to 1 indicates ATA drive error register bits are valid.
8
—
Reserved
9
HUT
Host UDMA burst Terminate—Software can terminate UDMA burst prematurely by setting
this bit. Bits 15 through 10 are unaffected and retain previous values.
this bit. Bits 15 through 10 are unaffected and retain previous values.
10
FR
FIFO Reset—Hardware resets FIFO when the direction is switched from Tx to Rx. No
hardware reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling
it for Tx. When bit 10 is set, FIFO is being reset and bits 15, 14, 13, 12, 11, 9 and 8 are
invalid.
hardware reset is done for Rx to Tx switch. Software must verify FIFO is empty before filling
it for Tx. When bit 10 is set, FIFO is being reset and bits 15, 14, 13, 12, 11, 9 and 8 are
invalid.
11
FE
Enable FIFO flush in Rx mode—For all commands except DEVICE RESET, this register is
written only when the ATA drive status register bits BSY and DRQ equal 0 and DMACK is not
asserted. If this register is written when BSY or DRQ bits are set to 1, the result is
indeterminate except for the DEVICE RESET command.
written only when the ATA drive status register bits BSY and DRQ equal 0 and DMACK is not
asserted. If this register is written when BSY or DRQ bits are set to 1, the result is
indeterminate except for the DEVICE RESET command.
Register content is not valid when drive is in sleep mode.