Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
13-8
Freescale Semiconductor
BestComm DMA Registers—MBAR+0x1200
13.15.7
SDMA Interrupt Mask Register—MBAR + 0x1218
Bit
Name
Description
0
DBG
Debug
1:2
—
Reserved
3
TEA
A TEA has been received by the currently running task. The corresponding
task number is written in the Error Task Number field
4:7
Etn[3:0]
Error Task Number: when a TEA is received by the currently executing task its
corresponding number is indicated here . If the TEA bit of the PtdControl register
is set then the task will not be halted. If the TEA Msk bit in the Mask register is
set then no interrupt to the core will be generated.
8:15
EU[7-0]
Execution Unit: only EU3 is valid for MPC5200B
16:31
TASK[15:0]
Each bit corresponds to an interrupt source defined by the task number or execution unit.
This register contains a registered copy of the interrupt signal that the interrupting source
generates. The corresponding bit in the register reflects the state of the interrupt signal
even if the corresponding mask bit is set. An interrupt is masked by setting the
corresponding bit in the IntMask register. A bit is cleared by writing 1 to that bit location.
Writing 0 has no effect. At system reset, all bits are initialized to logic 0.
This register contains a registered copy of the interrupt signal that the interrupting source
generates. The corresponding bit in the register reflects the state of the interrupt signal
even if the corresponding mask bit is set. An interrupt is masked by setting the
corresponding bit in the IntMask register. A bit is cleared by writing 1 to that bit location.
Writing 0 has no effect. At system reset, all bits are initialized to logic 0.
0 = The corresponding interrupt source is not pending.
1 = The corresponding interrupt source is pending.
Table 13-7. SDMA Interrupt Mask Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
DBG
Reserved
TEA
Msk
Reserved
EU[7:0]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
TASK[15:0]
W
RESET:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit
Name
Description
0
DBG
Debug: set to ‘1’ to mask the “debug” interrupt (see the SDMA Debug Control Register)
1:2
—
Reserved
3
TEA Msk
TEA Mask: set to ‘1’ to mask the TEA. If set to ‘1’ and a TEA is received in the currently
executing Task an interrupt is generated.
executing Task an interrupt is generated.
4:7
—
Reserved
8:15
EU[x]
Execution Unit: Only EU3 is present in MPC5200B
16:31
TASK[15:0]
Each bit corresponds to an interrupt source defined by the task number or execution unit.
An interrupt is masked by setting the corresponding bit. At system reset, all bits are
initialized to logic 1.
An interrupt is masked by setting the corresponding bit. At system reset, all bits are
initialized to logic 1.
0 = The corresponding interrupt source is not masked.
1 = The corresponding interrupt source is masked (no interrupt is generated).