Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
15-42
Freescale Semiconductor
PSC Registers—MBAR + 0x2000, 0x2200, 0x2400, 0x2600, 0x2800, 0x2C00
15.2.40
Tx FIFO Control (0x88)—TFCNTL
15.2.41
Tx FIFO Alarm (0x8E)—TFALARM
15.2.42
Tx FIFO Read Pointer (0x92)—TFRPTR
14
ALARM
The FIFO is requesting service from either BestComm or CPU. See
15
EMPTY
FIFO Empty. The FIFO is completely empty.
Table 15-67. Tx FIFO Control (0x88)
msb 0
1
2
3
4
5
6
7 lsb
R
Reserved
WFR
COMP
FRAME
GR[2:0]
W
RESET:
0
0
0
0
1
0
0
1
Bit
Name
Description
0:1
—
Reserved
2
WFR
Write frame. Not applicable for PSC FIFOs, since the PSCs do not recognize frame formats in
the serial data stream.
the serial data stream.
3
COMP
Re-enable requests on frame transmission completion. Not applicable to PSC FIFO’s, since
the PSCs do not recognize frame formats in the serial data stream.
the PSCs do not recognize frame formats in the serial data stream.
4
FRAME
Frame mode enable. THIS BIT MUST BE CLEARED BY WRITING A ‘0’ TO IT, since the PSCs
do not recognize frame formats in the serial data stream.
do not recognize frame formats in the serial data stream.
5:7
GR[2:0]
Last transfer granularity. Four times this value is the amount of data remaining in the FIFO at
which the ALARM bit in the status register will go low/inactive. See
which the ALARM bit in the status register will go low/inactive. See
for details.
Table 15-68. Tx FIFO Alarm (0x8E)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
ALARM
W
RESET:
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
Bit
Name
Description
0:3
—
Reserved
4:15
ALARM
“Almost empty” threshold level. Amount of data remaining in the Tx FIFO at which the ALARM
bit in the status register goes high/active. See
bit in the status register goes high/active. See
for details
Table 15-69. Tx FIFO Read Pointer (0x92)
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15 lsb
R
Reserved
R_PTR
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description