Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
18-18
Freescale Semiconductor
I
2
C Interface Registers
•
To the RX requestor at SDMA, if RE is set to 1.
Typically, only one (or none) of the above destinations would be specified. Although, it may be useful to send an interrupt to both the CPU
and SDMA. Selecting between TX and RX is based on whether the module is:
and SDMA. Selecting between TX and RX is based on whether the module is:
•
sending data (master or slave TX)
•
receiving data (master or slave RX)
Individual requests trigger different SDMA tasks. Reset condition is, IE set and all other enable bits clear.
The BNBE bit lets the module generate an interrupt when the bus becomes not-busy. This implies receipt of a STOP condition, for which the
module normally does not generate an interrupt. Because bus-not-busy is an idle condition, it is necessary for software responding to this
interrupt to clear the BNBE bit to clear the interrupt condition. Otherwise, the interrupt condition persists until another I
module normally does not generate an interrupt. Because bus-not-busy is an idle condition, it is necessary for software responding to this
interrupt to clear the BNBE bit to clear the interrupt condition. Otherwise, the interrupt condition persists until another I
2
C transaction is
initiated.
18.3.7
I
2
C Filter Register (MIFR)—MBAR + 0x3D24
Table 18-9. I
2
C Filter Register
msb 0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
Resv
Resv
Resv
Resv
FR3
FR2
FR1
FR0
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31 lsb
R
Reserved
W
RESET:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit
Name
Description
0:3
—
Reserved
4:7
FR[7:4]
Bits 7 to 4 contain the programming controls for the width of glitch (in terms of IPBUS clock
cycles) that the filter should absorb, that is, the filter will not let pass glitches less than or
equal to this width setting.
cycles) that the filter should absorb, that is, the filter will not let pass glitches less than or
equal to this width setting.
FR[]
3210
0000 - No Filter / Bypass
0001 - Filter glitches up to width of 1 IPBUS clock cycle
0010 - Filter glitches up to width of 2 IPBUS clock cycles
0011 - Filter glitches up to width of 3 IPBUS clock cycles
0100 - Filter glitches up to width of 4 IPBUS clock cycles
0101 - Filter glitches up to width of 5 IPBUS clock cycles
0110 - Filter glitches up to width of 6 IPBUS clock cycles
0111 - Filter glitches up to width of 7 IPBUS clock cycles
1000 - Filter glitches up to width of 8 IPBUS clock cycles
1001 - Filter glitches up to width of 9 IPBUS clock cycles
1010 - Filter glitches up to width of 10 IPBUS clock cycles
1011 - Filter glitches up to width of 11 IPBUS clock cycles
1100 - Filter glitches up to width of 12 IPBUS clock cycles
1101 - Filter glitches up to width of 13 IPBUS clock cycles
1110 - Filter glitches up to width of 14 IPBUS clock cycles
1111 - Filter glitches up to width of 15 IPBUS clock cycles
8:31
—
Reserved