Freescale Semiconductor MPC5200B ユーザーズマニュアル
Memory Map / Register Definition
MPC5200B Users Guide, Rev. 1
Freescale Semiconductor
19-7
19.5.4
MSCAN Control Register 1 (CANCTL1)—MBAR + 0x0901 / 0x981
The MSCAN Control Register 1 provides for various control and handshake status information of the MSCAN module.
READ: Anytime
WRITE: Anytime when INITRQ = 1 and INITAK = 1, except CANE which is write once in normal modes and anytime in special modes
when the MSCAN is in Initialization Mode (INITRQ = 1 and INITAK = 1).
when the MSCAN is in Initialization Mode (INITRQ = 1 and INITAK = 1).
Table 19-4. MSCAN Control Register 1
msb 0
1
2
3
4
5
6
7 lsb
R
CANE
CLKSRC
LOOPB
LISTEN
Rsvd
WUPM
SLP
A
K
INIT
A
K
W
RESET:
0
0
0
1
0
0
0
1
Bit
Name
Description
0
CANE
MSCAN Enable
0 = MSCAN module is disabled
1 = MSCAN module is enabled
1
CLKSRC
MSCAN Clock Source—bit defines MSCAN module clock source (only for systems with a
system clock generation module.
system clock generation module.
0 = MSCAN clock source is the IP bus clock (IP CLK)
1 = MSCAN clock source is the oscillator clock (SYS_XTAL_IN)
NOTE: The two MSCAN modules can have different selected clock sources.
2
LOOPB
Loop-Back Self-Test Mode—when bit is set, MSCAN does an internal loop-back that can be
used for self test operation. Tx bit-stream output feeds back to receiver internally. RxCAN input
pin is ignored and TxCAN output goes to recessive state (logic ‘1’). MSCAN behaves as it does
normally when transmitting and treats its own transmitted message as a message received
from a remote node. In this state, MSCAN ignores bit sent during ACK slot in CAN frame
acknowledge field to ensure proper reception of its own message. Both Tx and Rx interrupts
are generated.
used for self test operation. Tx bit-stream output feeds back to receiver internally. RxCAN input
pin is ignored and TxCAN output goes to recessive state (logic ‘1’). MSCAN behaves as it does
normally when transmitting and treats its own transmitted message as a message received
from a remote node. In this state, MSCAN ignores bit sent during ACK slot in CAN frame
acknowledge field to ensure proper reception of its own message. Both Tx and Rx interrupts
are generated.
3
LISTEN
Listen-Only Mode—bit configures MSCAN as bus monitor. When bit is set, all valid CAN
messages with matching ID are received, but no acknowledgement or error frames are sent
out. In addition, error counters are frozen. Listen-only mode supports applications that require
“hot plugging” or throughput analysis. MSCAN is unable to transmit any messages, when
listen-only mode is active.
messages with matching ID are received, but no acknowledgement or error frames are sent
out. In addition, error counters are frozen. Listen-only mode supports applications that require
“hot plugging” or throughput analysis. MSCAN is unable to transmit any messages, when
listen-only mode is active.
0 = normal operation
1 = Listen Only Mode activated
4
—
Reserved
5
WUPM
WakeUp Mode—bit defines whether the integrated low-pass filter is applied to protect the
MSCAN from spurious WakeUp.
MSCAN from spurious WakeUp.
0 = MSCAN wakes-up the CPU after any recessive to dominant edge on the CAN bus and
WUPE=1 in CANCTL0
WUPE=1 in CANCTL0
1 = MSCAN wakes-up the CPU only in case of a dominant pulse on the bus which has a
length of T
length of T
wup
and WUPE=1 in CANCTL0