Freescale Semiconductor MPC5200B ユーザーズマニュアル
MPC5200B Users Guide, Rev. 1
19-12
Freescale Semiconductor
Memory Map / Register Definition
19.5.8
MSCAN Receiver Interrupt Enable Register (CANRIER)—MBAR + 0x0909 / 0x989
7
RXF
Receive Buffer Full—flag is set by MSCAN when a new message is shifted into RX FIFO.
Flag indicates whether the shifted buffer is loaded with a correctly received message
(matching identifier, matching cyclic redundancy code (CRC) and no other errors
detected). After CPU reads message from RxFG buffer in Rx FIFO, RxF flag must be
cleared to release the buffer.
Flag indicates whether the shifted buffer is loaded with a correctly received message
(matching identifier, matching cyclic redundancy code (CRC) and no other errors
detected). After CPU reads message from RxFG buffer in Rx FIFO, RxF flag must be
cleared to release the buffer.
A set RxF flag prohibits shifting of next FIFO entry into foreground buffer (RxFG). If not
masked, RX interrupt is pending while this flag is set.
masked, RX interrupt is pending while this flag is set.
To ensure data integrity, do not read the Rx buffer registers while RxF flag is cleared. For
MCUs with dual CPUs, reading Rx buffer registers while RxF flag is cleared may result in
a CPU fault condition.
MCUs with dual CPUs, reading Rx buffer registers while RxF flag is cleared may result in
a CPU fault condition.
0 = No new message available within the RxFG.
1 = The receiver FIFO is not empty. A new message is available in the RxFG.
Note: To ensure data integrity, do not read the receive buffer registers while the RXF flag
is cleared.For MCUs with dual CPUs, reading the receive buffer registers while the RXF
flag is cleared may result in a CPU fault condition.
is cleared.For MCUs with dual CPUs, reading the receive buffer registers while the RXF
flag is cleared may result in a CPU fault condition.
Note:
1.
Every flag has an associated interrupt enable bit in the CANRIER register. A flag can only be cleared:
•
when the condition that caused the setting is no longer valid.
•
by software writing 1 to the corresponding bit position.
Table 19-11. MSCAN Receiver Interrupt Enable Register
msb 0
1
2
3
4
5
6
7 lsb
R
WUPIE
CSCIE
RSTATE[1:0]
TSTATE[1:0]
OV
R
IE
RX
F
IE
W
RESET:
0
0
0
0
0
0
0
0
Bit
Name
Description
0
WUPIE
WakeUp Interrupt Enable
0 = No interrupt request is generated from this event.
1 = A WakeUP event causes a WakeUp interrupt request.
1
CSCIE
CAN Status Change Interrupt Enable
0 = No interrupt request is generated from this event
1 = A CAN Status Change event causes an error interrupt request
2:3
RSTATE[1:0]
Receiver Status Change Enable—bits control sensitivity level in which Rx state changes
cause CSCIF interrupts. Independent of the chosen sensitivity level, RSTATE flags still
indicate the actual Rx state and are only updated if no CSCIF interrupt is pending.
cause CSCIF interrupts. Independent of the chosen sensitivity level, RSTATE flags still
indicate the actual Rx state and are only updated if no CSCIF interrupt is pending.
00 = Do not generate CSCIF interrupt caused by Rx state changes.
01 = Generate CSCIF interrupt only if receiver enters or leaves “BusOff” state. Discard other
Rx state changes for generating CSCIF interrupt.
Rx state changes for generating CSCIF interrupt.
10 = Generate CSCIF interrupt only if receiver enters or leaves “RxErr” or “BusOff” state.
Discard other Rx state changes for generating CSCIF interrupt.
Discard other Rx state changes for generating CSCIF interrupt.
11 = Generate CSCIF interrupt on all Rx state changes.
Bit
Name
Description