Freescale Semiconductor MPC5200B ユーザーズマニュアル

Freescale Semiconductor

20-5

and reception. The MUX Interface provides the link between the BDLC digital section and the analog Physical Interface. The wave shaping, 
driving and digitizing of data is performed by the Physical Interface.

The Physical Interface is not implemented in the BDLC module and must be provided externally.

The main functional blocks of the BDLC module are explained in greater detail in the following 
sections. 

Use of the BDLC module in message networking fully implements the “SAE Standard J1850 Class 
B Data Communication Network Interface” specification.

The BDLC module has a total of 2 external pins.

The TXB pin serves as the transmit output channel for the BDLC module.

The RXB pin serves as the receive input channel for the BDLC module.

This section provides a detailed description of all memory and registers accessible to the end user.

This register is used to configure and control the BDLC module.

MBAR + 0x1300

BDLC Control Register

 1 (DLCBCR1)

R/W

MBAR + 0x1301

BDLC State Vector Register (DLCBSVR)

R

MBAR + 0x1304

BDLC Control Register

 2 (DLCBCR2)

R/W

MBAR + 0x1305

BDLC Data Register (DLCBDR)

R/W

MBAR + 0x1308

BDLC Analog Round Trip Delay Register (DLCBARD)

R/W

MBAR + 0x1309

BDLC Rate Select Register (DLCBRSR)

R/W

MBAR + 0x130C

BDLC Control Register (DLCSCR)

R/W

MBAR + 0x130D

BDLC Status Register (DLCBSTAT)

R