Freescale Semiconductor MPC5200B ユーザーズマニュアル

20-12

Freescale Semiconductor

The extra logic 1s are an enhancement to the J1850 protocol which forces a byte boundary condition 
fault. This is helpful in preventing noise on the J1850 bus from corrupting a message.

This register is used to pass the data to be transmitted to the J1850 bus from the CPU to the BDLC module. It is also used to pass data received 
from the J1850 bus to the CPU. 

READ: any time

WRITE: any time

D7:D0 

—

 Receive/Transmit Data (Bits 7 - 0)

While transmitting, each data byte (after the first one) should be written only after a “Tx Data Register Empty” (TDRE) interrupt has occurred, 
or the BDLC State Vector Register register has been polled indicating this condition.

Data read from this register will be the last data byte received from the J1850 bus. This received data should only be read after a “Rx Data 
Register Full” (RDRF) or “Received IFR byte” (RXIFR) interrupt has occurred or the BDLC State Vector Register register has been polled 
indicating either of these two conditions.

The BDLC Data Register is double buffered via a transmit shadow register and a receive shadow register. After the byte in the transmit shift 
register has been transmitted, the byte currently stored in the transmit shadow register is loaded into the transmit shift register. Once the 
transmit shift register has shifted the first bit out, the TDRE flag is set, and the shadow register is ready to accept the next byte of data. 

The receive shadow register works similarly. Once a complete byte has been received, the receive shift register stores the newly received byte 
into the receive shadow register. The RDRF flag (or RXIFR flag if the received byte is part of an IFR) is set to indicate that a new byte of data 
has been received. The programmer has one BDLC module byte reception time to read the shadow register and clear the RDRF or RXIFR 
flag before the shadow register is overwritten by the newly received byte.

If the user writes the first byte of a message to be transmitted to the BDLC Data Register and then determines that a different message should 
be transmitted, the user can write a new byte to the BDLC Data Register up until the transmission begins.This new byte will replace the 
original byte in the BDLC Data Register.

From the time a byte is written to the BDLC Data Register until it is transferred to the transmit shift register, the transmit shadow register is 
considered full and the byte pending transmission. If one of the IFR transmission control bits (TSIFR, TMIFR1, or TMIFR0 in BDLC Control 
Register 2) is also set, the byte is pending transmission as an IFR. A byte pending transmission will be flushed from the transmit shadow 
register and the transmission canceled if one of the following occurs: a loss of arbitration or transmitter error on the byte currently being 
transmitted; a symbol error, framing error, bus fault, or BREAK symbol is received. If the byte pending transmission is an IFR byte, the 
reception of a message with a CRC error will also cause the byte in the transmit shadow register to be flushed. 

To abort an in-progress transmission, the programmer should simply stop loading more data into the BDLC Data Register. This will cause a 
transmitter underrun error and the BDLC module will automatically disable the transmitter on the next non-byte boundary. This means that 
the earliest a transmission can be halted is after at least one byte (plus two extra 1-bits) has been transmitted. The receiver will pick this up as 
an error and relay it in the State Vector Register as an invalid symbol error.

This register is used to program the BDLC module so that it compensates for the round trip delays of different external transceivers. Also the 
polarity of the receive pin (RXB) is set in this register.

msb  0

1

2

3

4

5

6

7  lsb

R

D7

D6

D5

D4

D3

D2

D1

D0

W

RESET:

0

0

0

0

0

0

0

0