Freescale Semiconductor MPC5200B ユーザーズマニュアル

20-48

Freescale Semiconductor

The first step necessary for initializing the BDLC module following an MCU reset is to write the desired values to each of the BDLC module 
control registers. This is best done by storing predetermined initialization values directly into these registers. The following description 
outlines a basic flow for initializing the BDLC module. This basic flow does not detail more elaborate initialization routines, such as 
performing digital and analog loopback tests before enabling the BDLC module for SAE J1850 communication. However, from the following 
descriptions and the BDLC module specification, the user should be able to develop routines for performing various diagnostic procedures 
such as loopback tests.

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Step 1 - Initialize BDLC Analog Round Trip Delay Register

Begin initialization of the configuration bits by writing the desired analog transceiver configuration data into the BDLC Analog 
Round Trip Delay Register. Following this write to BDLC Analog Round Trip Delay Register, all of these bits will become read 
only.

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Step 2- Initialize BDLC Baud Rate Select Register

The next step in BDLC module initialization is to write the desired bus clock divisor minus one into the BDLC Baud Rate Select 
RegisterBDLC Baud Rate Select Register. The divisor should be chosen to generate a 1 MHz or 1.048576 MHz mux interface clock 
(f

bdlc

). Following this write to BDLC Baud Rate Select Register, all of these bits will become read only.

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Step 3- Initialize BDLC Control Register 2

The next step in BDLC module initialization should be writing the configuration bits into the BDLC Control Register 2 register. 
This initialization description assumes that the BDLC module will be put into normal mode (not 4X mode), and that the BDLC 
module should not yet exit either digital or analog loopback mode. Therefore, this step should write SMRST and DLOOP as logic 
ones, 4XE as a logic zero, write NBFS to the desired level, and write TEOD, TSIFR, TMIFR1 and TMIFR0 as logic zeros. These 
last four bits MUST be written as logic zeros in order to prevent undesired operation of the BDLC module.

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Step 4- Initialize BDLC Control Register 1

The next step in BDLC module initialization is to write the configuration bits in BDLC Control Register 1. The CLKS bit should 
be written to its desired values at this time, following which it will become read-only. The IE bit should be written as a logic zero 
at this time so BDLC module interrupts of the CPU will remain masked for the time being. The IMSG bit should be written as a 
logic one to prevent any receive events from setting the BDLC State Vector Register until a valid SOF (or BREAK) symbol has 
been received by the BDLC module.

Once the configuration bits have been written to the desired values, the BDLC module should be taken out of loopback and connected to the 
SAE J1850 bus. This is done by clearing the DLOOP bit and then setting the BDLCE bit in the BDLC Control Register.

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Step 5- Perform Loopback Tests (optional)

Once the BDLC module is configured for desired operation, the user may wish to perform digital and/or analog loopback tests to 
determine the integrity of the link to the SAE J1850 network. This would involve leaving the DLOOP bit (BDLC Control Register 
2) set, setting the BDLCE bit, preforming the desired loopback tests and finally exiting digital loopback mode by clearing DLOOP 
in the BDLC Control Register 2.

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Step 6- Exit Loopback Mode and enable the BDLC module

If loopback mode tests are not to be preformed the BDLC module can be removed from digital loopback mode by clearing the 
DLOOP bit. The BDLC module can then be enabled by setting the BDLCE bit in the BDLC Control Register.

Once DLOOP is cleared and BDLCE is set, the BDLC module is ready for SAE J1850 communication. However, to ensure that the 
BDLC module does not attempt to receive a message already in progress or to transmit a message while another device is 
transmitting, the BDLC module must first observe an EOF symbol on the bus before the receiver will be activated. To activate the 
transmitter, the BDLC module will need to observe an Inter-Frame Separator symbol.

The final step in readying the BDLC module for proper communication is to clear any pending interrupt sources and then, if desired, enable 
BDLC module interrupts of the CPU.

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Step 7- Clear Pending BDLC Interrupts

In order to ensure that the BDLC module does not immediately generate a CPU interrupt when interrupts are enabled, the user 
should read the BDLC State Vector Register to determine if any BDLC module interrupt sources are pending before setting the IE 
bit in the BDLC Control Register 1. If the BDLC State Vector Register reads as a %00000000, no interrupts are pending and the 
user is free to enable BDLC interrupts, if desired.

If the BDLC State Vector Register indicates that an interrupt is pending, the user should perform whatever actions are necessary to 
clear the interrupt source before enabling the interrupts. Whether any interrupts are pending will depend primarily upon how much