IBM powerpc 750gx ユーザーズマニュアル
User’s Manual
IBM PowerPC 750GX and 750GL RISC Microprocessor
Memory Management
Page 182 of 377
gx_05.fm.(1.2)
March 27, 2006
the memory subsystem. The MMUs record whether the translation is for an instruction or data access,
whether the processor is in user or supervisor mode, and for data accesses, whether the access is a load or
a store operation.
whether the processor is in user or supervisor mode, and for data accesses, whether the access is a load or
a store operation.
The MMUs use this information to appropriately direct the address translation and to enforce the protection
hierarchy programmed by the operating system. (Section 4.3, Exception Processing, on page 156 describes
the MSR, which controls some of the critical functionality of the MMUs.)
hierarchy programmed by the operating system. (Section 4.3, Exception Processing, on page 156 describes
the MSR, which controls some of the critical functionality of the MMUs.)
The figures show how address bits A[20–26] index into the on-chip instruction and data caches to select a
cache set. The remaining physical address bits are then compared with the tag fields (comprised of bits
PA[0–19]) of the eight selected cache blocks to determine if a cache hit has occurred. In the case of a cache
miss on the 750GX, the instruction or data access is then forwarded to the L2 tags to check for an L2 cache
hit. In case of a miss, the access is forwarded to the bus interface unit, which initiates an external memory
access.
cache set. The remaining physical address bits are then compared with the tag fields (comprised of bits
PA[0–19]) of the eight selected cache blocks to determine if a cache hit has occurred. In the case of a cache
miss on the 750GX, the instruction or data access is then forwarded to the L2 tags to check for an L2 cache
hit. In case of a miss, the access is forwarded to the bus interface unit, which initiates an external memory
access.