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Video RAM Cacheable
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Transfer Mode
In this item you can select AGP transfer mode Auto/4X/1X the Default setting is Auto.
Select Enabled allows caching of the video BIOS, resulting in better system performance.
However, if any program writes to this memory area, a system error may result. The settings
are: Enabled and Disabled.
Memory Hole At 15M-16M
You can reserve this area of system memory for ISA adapter ROM. When this area is
reserved, it cannot be cached. The user information of peripherals that need to use this area of
system memory usually discusses their memory requirements. The settings are: Enabled and
Disabled.
Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay transactions cycles.
Select Enabled to support compliance with PCI specification version 2.1. The settings are:
Enabled and Disabled.
AGP Transfer Mode
In this item you can select AGP transfer mode Auto/4X/1X the Default setting is Auto.
3-6-1 DRAM Timing Settings
CMOS Setup Utility – Copyright(C) 1984-2002 Award Software
DRAM Timing Settings
Item Help
Auto Configuration Standard
SDRAM CAS Latency Time 2.5
SDRAM Cycle Time 7
SDRAM RAS# to CAS# Delay 3
SDRAM RAS# Precharge Time 3
SDRAM CAS Latency Time 2.5
SDRAM Cycle Time 7
SDRAM RAS# to CAS# Delay 3
SDRAM RAS# Precharge Time 3
Menu Level >>
↑↓→←
Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
SDRAM CAS Latency Time
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
Note: Change these settings only if you are familiar with the chipset.
SDRAM RAS# to CAS# Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T, 3T and 4T.
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed. Fast gives faster performance; and Slow gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 2T, 3T and 4T.
SDRAM RAS# Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date. Fast
gives faster performance; and Slow gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T, 3T and 4T.
3-7 Integrated Peripherals