B+B SmartWorx APPN551 ユーザーズマニュアル
APPN-TT551 Databook
B&B Electronics, Inc.
15
6.0 SPI Interface
The following section details the SPI interface specification for both hardware timing and
SPI protocol. The device is a SPI slave and requires a compatible SPI master for
operation.
SPI protocol. The device is a SPI slave and requires a compatible SPI master for
operation.
6.1
Pin-out
When the SPI interface is enabled, through the CLI or web interface, the
following pins are assigned for communication.
following pins are assigned for communication.
Table 10 - SPI Pinout Details
Pin Definition
SPI
Master In Slave Out (MISO)
28
Master Out Slave In (MOSI)
24
SPI Interrupt (SPI_INT)
22
SPI Clock (SPI_CLK)
18
SPI Select (/SPI_SEL)
12
Table 11 - SPI Signal Descriptions
Pin Definition
Description
Master In Slave Out (MISO)
Serial Data OUT; must be connected to the serial data in of
the master.
the master.
Master Out Slave In (MOSI)
Serial Data IN; Must be connected to the serial data out of the
master.
master.
SPI Interrupt (SPI_INT)
Interrupt signal driver by slave see Table 16 for details of
operation.
operation.
SPI Clock (SPI_CLK)
SPI clock sourced from the master.
SPI Select (/SPI_SEL)
Enable the SPI slave, sourced from the master. Active low
signal.
signal.
Use of the SPI interface is mutually exclusive with the use of UART1 and the
Ethernet ports, as the API interface reuses pins from both of these interfaces.
Ethernet ports, as the API interface reuses pins from both of these interfaces.