Computime Limited CT-EM2531 ユーザーズマニュアル
EM2531/01
ZigBee- Ready RF Transceiver Modules
All rights reserved. Property of Computime Ltd.
8 / 13 V1.0
SIF Module Programming and Debug Interface
SIF is a synchronous serial interface developed by Cambridge Consultants Ltd. It is
the primary programming and debug interface of the CT-EM2500. The SIF module
allows external devices to read and write memory-mapped registers in real-time
without changing the functionality or timing of the XAP2b core.
The SIF interface provides the following:
z
the primary programming and debug interface of the CT-EM2500. The SIF module
allows external devices to read and write memory-mapped registers in real-time
without changing the functionality or timing of the XAP2b core.
The SIF interface provides the following:
z
IC production test (especially analog)
z
PCB production test
z
XAP2b code development
z
Product control and characterization
The pins are:
z
SIF_LOADB
z
SIF_CLK
z
SIF_MOSI
z
SIF_MISO
The maximum serial shift speed for the SIF interface is 48MHz. SIF interface
accesses can be initiated even when the chip is in idle and deep sleep modes. An
edge on SIF_LOADB wakes the chip to allow SIF cycles.
accesses can be initiated even when the chip is in idle and deep sleep modes. An
edge on SIF_LOADB wakes the chip to allow SIF cycles.
Power Management
The CT-EM2500 supports three different power modes: processor ACTIVE,
processor IDLE, and DEEP SLEEP.
The IDLE power mode stops code execution of the XAP2b until any interrupt occurs
or an external SIF wakeup command is seen. All peripherals including the radio
continue to operate normally.
The DEEP SLEEP power mode powers off most of the module but leaves the critical
chip functions, such as the GPIO pads and RAM powered by the High Voltage Supply
(VDD_PADS). The module can be woken by configuring the sleep timer to generate
an interrupt after a period of time, using an external interrupt, or with the SIF interface.
Activity on a serial interface may also be configured to wake the module, though
actual reception of data is not re-enabled until the module has finished waking up.
Depending on the speed of the serial data, it is possible to finish waking up in the
middle of a byte. Care must be taken to reset the serial interface between bytes and
discard any garbage data before the rest. Another condition for wakeup is general
activity on GPIO pins.
processor IDLE, and DEEP SLEEP.
The IDLE power mode stops code execution of the XAP2b until any interrupt occurs
or an external SIF wakeup command is seen. All peripherals including the radio
continue to operate normally.
The DEEP SLEEP power mode powers off most of the module but leaves the critical
chip functions, such as the GPIO pads and RAM powered by the High Voltage Supply
(VDD_PADS). The module can be woken by configuring the sleep timer to generate
an interrupt after a period of time, using an external interrupt, or with the SIF interface.
Activity on a serial interface may also be configured to wake the module, though
actual reception of data is not re-enabled until the module has finished waking up.
Depending on the speed of the serial data, it is possible to finish waking up in the
middle of a byte. Care must be taken to reset the serial interface between bytes and
discard any garbage data before the rest. Another condition for wakeup is general
activity on GPIO pins.