Multi-Tech Systems 92U10E06831 ユーザーズマニュアル
PART 3 – Analog SocketModems
Chapter 8 – SocketModem (MT5692SMI)
Multi-Tech Systems, Inc. Universal Socket Hardware Guide for Developers (S000342M)
136
Register Functional Definitions
The following table delineates the assigned bit functions for the twelve internal registers. The assigned bit functions are more
fully defined in the following paragraphs.
fully defined in the following paragraphs.
Internal Registers
Register
No.
Register
Name
BIT No.
7
6
5
4
3
2
1
0
7 Scratch
Register
(SCR)
Scratch Register
6 Modem
Status
Register (MSR)
Data
Carrier
Detect
(DCD)
(DCD)
Ring
Indicator
(RI)
Data Set
Ready
(DSR)
Clear to
Send
CTS)
CTS)
Delta Data
Carrier
Detect
(DDCD)
Trailing
Edge of Ring
Indicator
(TERI)
Delta Data
Set Ready
Set Ready
(DDSR)
Delta Clear
to Send
(DCTS)
(DCTS)
5 Line
Status
Register (LSR)
RX FIFO
Error
Transmitter
Empty
(TEMT)
Transmitter
Buffer
Register
Empty
(THRE)
Break
Interrupt
(BI)
Framing
Error
(FE)
(FE)
Parity
Error
(PE)
Overrun
Error
(OE)
Receiver
Data
Ready
(DR)
4 Modem
Control
Register (MCR)
0 0 0
0
Out
2
Out
1
Request
to Send
(RTS)
Data
Terminal
Ready
(DTR)
3 Line
Control
Register (LCR)
Divisor
Latch
Access Bit
(DLAB)
Set
Break
Stick
Parity
Even
Parity
Select
(EPS)
Parity
Enable
(PEN)
Number
of Stop
Bits
(STB)
Word
Length
Select
Bit 1
(WLS1)
Word
Length
Select
Bit 0
(WLSO)
2 Interrupt
Identify
Register (IIR)
(Read Only)
(Read Only)
FIFOs
Enabled
FIFOs
Enabled
0 0
Pending
Interrupt ID
Bit 2
Pending
Interrupt ID
Bit 1
Pending
Interrupt ID
Bit 0
“0” if
Interrupt
Pending
Pending
2 FIFO
Control
Register (FCR)
(Write Only)
(Write Only)
Receiver
Trigger
MSB
Receiver
Trigger
LSB
Reserved Reserved
DMA
Mode
Select
TX FIFO
Reset
RX FIFO
Reset
FIFO
Enable
1
(DLAB = 0)
Interrupt Enable
Register (IER)
Register (IER)
0 0 0
0
Enable
Modem
Status
Interrupt
(EDSSI)
(EDSSI)
Enable
Receiver
Line Status
Interrupt
(ELSI)
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETBEI)
Enable
Received
Data
Available
Interrupt
(ERBFI)
0
(DLAB = 0)
Transmitter Buffer
Register
(THR)
Register
(THR)
Transmitter FIFO Buffer Register (Write Only)
0
(DLAB = 0)
Receiver Buffer
Register (RBR)
Register (RBR)
Receiver FIFO Buffer Register (Read Only)
1
(DLAB = 1)
Divisor Latch MSB
Register (DLM)
Register (DLM)
Divisor Latch MSB
0
(DLAB = 1)
Divisor Latch LSB
Register (DLL)
Register (DLL)
Divisor Latch LSB
Preliminary
Confidential