Intel 2760QM FF8062701065300 ユーザーズマニュアル
製品コード
FF8062701065300
Datasheet, Volume 1
5
7.2
Signal Group Summary ...................................................................................... 56
7.3
Power-On Configuration (POC) Options................................................................. 59
7.4
Absolute Maximum and Minimum Ratings ............................................................. 60
7.4.1
7.4.1
Storage Conditions Specifications ............................................................. 60
7.5
DC Specifications .............................................................................................. 61
7.5.1
7.5.1
Voltage and Current Specifications............................................................ 61
7.5.2
Die Voltage Validation ............................................................................. 63
7.5.2.1
7.5.2.1
VCC Overshoot Specifications ..................................................... 63
7.5.3
Signal DC Specifications .......................................................................... 64
7.5.3.1
7.5.3.1
PCI Express* DC Specifications ................................................... 69
7.5.3.2
DMI2/PCI Express* DC Specifications .......................................... 69
7.5.3.3
Reset and Miscellaneous Signal DC Specifications .......................... 69
8
Processor Land Listing............................................................................................. 71
9
Package Mechanical Specifications ........................................................................ 119
Figures
1-1
Processor Platform Block Diagram Example........................................................... 10
1-2
PCI Express* Lane Partitioning and Direct Media Interface Gen 2 (DMI2) .................. 12
2-1
PCI Express* Layering Diagram........................................................................... 18
2-2
Packet Flow through the Layers........................................................................... 18
4-1
Idle Power Management Breakdown of the Processor Cores..................................... 31
4-2
Thread and Core C-State Entry and Exit .............................................................. 31
4-3
Package C-State Entry and Exit ........................................................................... 35
7-1
Input Device Hysteresis ..................................................................................... 50
7-2
VR Power-State Transitions................................................................................. 54
7-3
VCC Overshoot Example Waveform...................................................................... 63
Tables
1-1
Terminology ..................................................................................................... 14
1-2
Reference Documents ........................................................................................ 16
4-1
System States .................................................................................................. 27
4-2
Package C-State Support.................................................................................... 28
4-3
Core C-State Support......................................................................................... 28
4-4
System Memory Power States ............................................................................. 29
4-5
DMI2/PCI Express* Link States ........................................................................... 29
4-6
G, S, and C State Combinations .......................................................................... 30
4-7
P_LVLx to MWAIT Conversion ............................................................................. 32
4-8
Coordination of Core Power States at the Package Level ......................................... 35
4-9
Package C-State Power Specifications .................................................................. 37
6-1
Memory Channel DDR0, DDR1, DDR2, DDR3......................................................... 41
6-2
Memory Channel Miscellaneous ........................................................................... 42
6-3
PCI Express* Port 1 Signals ................................................................................ 42
6-4
PCI Express* Port 2 Signals ................................................................................ 43
6-5
PCI Express* Port 3 Signals ................................................................................ 43
6-6
PCI Express* Miscellaneous Signals ..................................................................... 44
6-7
DMI2 to Port 0 Signals ....................................................................................... 44
6-8
PECI Signals ..................................................................................................... 44
6-9
System Reference Clock (BCLK{0/1}) Signals ....................................................... 44