Tymphany HK Limited DWHP83 ユーザーズマニュアル

                                                        

                   

 

Data Sheet 
Rev0.1 12/13/2017 

 

Page 4 of 9 

 

• Up to four stereo audio channels, fully bidirectional, up to 24-bit/96 ksps uncompressed audio 
• Low latency <20ms for real-time audio and lip sync 
• Low latency compression algorithm - optimized for voice applications, headphones 
• Inter-speaker synchronization; Low-jitter audio clock sync 
• Programmable digital audio gain 

• 22Mbps Bandwidth in  5.8 GHz Bands 
• Point-to-Point and Point-to-Multipoint 
• Bidirectional data channel (100 kbps) 
• Simple Pairing and Association Function 
• 4 I

2

S Data pins, each provided with their own pair of BCK/LRCK signals or stereo S/PDIF input/output 

• Master and Slave I2C bus for external control functions 

• Enhanced robustness against both in- and out of band interferers like: Wi-Fi and cordless phones 
• Coexistence with 802.11a, b, g and n 
• Automatic receiver antenna diversity minimizes fading and multi-path effects 
• Link quality monitoring 
• Soft audio muting under poor link circumstances 

• Low power consumption 
• Automatic RF output power control 
• Power Down Duty Cycle mode: If no link is established, modules (both TX and RX) will enter power down 
  mode  

The DARR83 integrates an 8052 MCU. This includes the following features: 
• 45 kByte Code RAM 
• 8 kByte Data RAM 
• 4 Timer/Counters 
• UART 
 

The digital audio clock synchronization is an additional more cost effective method for synchronization of audio 
samples on the receiving side with respect to the transmitted audio samples. The digital clock 
synchronization feature works for output audio sample rates of 96 and 48 ksps.