InVue ED0991 ユーザーズマニュアル
ED0991 Module, Users Manual
Key Features
The ED0991 is a modular transceiver to meet the requirements of 47 C.F.R. § 15.212
(i) The radio elements of the ED0991 have their own shielding.
(ii) The ED0991 does not have modulation/data inputs. The modulation is generated internal and
(ii) The ED0991 does not have modulation/data inputs. The modulation is generated internal and
the modulation type is fixed as BPM w/ BPSK. The data rates are fixed and set to the module via
an SPI interface to the host MCU.
an SPI interface to the host MCU.
(iii) The modular transmitter has its own power supply regulator.
An IEEE802.15.4-2011 UWB compliant wireless transceiver module based on DecaWave’s DW1000 IC.
Fully coherent receiver for maximum range and accuracy.
Designed to comply with FCC & ETSI UWB spectral masks
Supply voltage 2.8V to 3.6V
SPI Interface to host processor
Key Benefits
High immunity to multipath fading – allows reliable communications in high fading environments
Low power consumption allows operation from batteries for long periods*
Small physical size allows the implementation of cost-effective solutions in RTLS and WSN
Integrated antenna allows simple product implementation – no RF design required
Integration of DW1000 IC, antenna, power management and clock control simplifies design integration
Very precise location of tagged objects delivers enterprise efficiency gains and cost reductions
Long LOS and NLOS range reduces amount of infrastructure required to deploy systems
Low power consumption reduces the need to replace batteries and lowers system lifetime costs
Standards based solution (IEEE802.15.4-2011), eases proliferation
Low cost allows cost-effective implementation of solutions
The ED0991 module interfaces to an application microcontroller via SPI bus. Physical and MAC layer functionality
are accessed via the SPI bus, through addressable registers as well as execution commands. Data received or to be
transmitted are also accessed through the SPI bus and are implemented as a FIFO register (64 bytes each for TX
and RX). To transmit, a frame of data is placed in the FIFO, this may include a destination address. A transmit
command is given, which will transmit the data according to the initial setup of the registers. To receive data a
receive command is given, which will listen for a transmission and when one occurs put the received frame in the
FIFO. When neither transmit nor receive is required the device can enter either an Idle mode, from which it can
quickly re-enter receive or transmit mode or it can enter a low power sleep mode, from which a crystal startup is
also required prior to transmit or receive operation.
A block diagram is given for the ED0991 module in Figure 1.
are accessed via the SPI bus, through addressable registers as well as execution commands. Data received or to be
transmitted are also accessed through the SPI bus and are implemented as a FIFO register (64 bytes each for TX
and RX). To transmit, a frame of data is placed in the FIFO, this may include a destination address. A transmit
command is given, which will transmit the data according to the initial setup of the registers. To receive data a
receive command is given, which will listen for a transmission and when one occurs put the received frame in the
FIFO. When neither transmit nor receive is required the device can enter either an Idle mode, from which it can
quickly re-enter receive or transmit mode or it can enter a low power sleep mode, from which a crystal startup is
also required prior to transmit or receive operation.
A block diagram is given for the ED0991 module in Figure 1.