Dataram 2GB DDR2 DTM63367A ユーザーズマニュアル
製品コード
DTM63367A
DTM63367
2 GB - 256Mx64, 240-Pin Unbuffered DDR2 DIMM
Document 06926, Revision A, 18-DEC-07, Dataram Corporation
© 2007
Page 1
Features
Description
240-pin JEDEC-compliant DIMM, 133.35 mm wide by 30 mm high
Operating Voltage: 1.8 V ±0.1
I/O Type: SSTL_18
Data Transfer Rate: 6.4 Gigabytes/sec
Data Bursts: 4 or 8 bits, Sequential or Interleaved ordering
Programmable I/O driver strength (OCD)
Programmable On-Die Termination (ODT)
Programmable CAS Latency: 4 or 5
Differential/Redundant Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 14/10/3
DTM63367 is an Unbuffered 256Mx64
memory module, which conforms to
JEDEC's DDR2, PC2-6400 standard. The
assembly is comprised of two Ranks. Each
Rank is comprised of eight 128Mx8 DDR2
SDRAMs. One 2K-bit EEPROM is used for
Serial Presence Detect.
Both output driver strength and input
termination impedance are programmable to
maintain signal integrity on the I/O signals.
memory module, which conforms to
JEDEC's DDR2, PC2-6400 standard. The
assembly is comprised of two Ranks. Each
Rank is comprised of eight 128Mx8 DDR2
SDRAMs. One 2K-bit EEPROM is used for
Serial Presence Detect.
Both output driver strength and input
termination impedance are programmable to
maintain signal integrity on the I/O signals.
Fully RoHS Compliant
Pin Configuration
Pin Description
Front Side
Back Side
Name
Function
1 VREF
31 DQ19
61 A4
91 VSS
121 VSS
151 VSS
181 VDD
211 DM5
CB[7:0]
Data Check Bits
2 VSS
32 VSS
62 VDD
92 /DQS5 122 DQ4
152 DQ28
182 A3
212 NC
DQ[63:0]
Data Bits
3 DQ0
33 DQ24
63 A2
93 DQS5 123 DQ5
153 DQ29
183 A1
213 VSS
DQS[8:0], /DQS[8:0]
Differential Data Strobes
4 DQ1
34 DQ25
64 VDD
94 VSS
124 VSS
154 VSS
184 VDD
214 DQ46
DM[8:0]
Data Mask
5 VSS
35 VSS
65 VSS
95 DQ42 125 DM0
155 DM3
185 CK0
215 DQ47
CK[2:0], /CK[2:0]
Differential Clock Inputs
6 /DQS0 36 /DQS3
66 VSS
96 DQ43 126 NC
156 NC
186 /CK0
216 VSS
CKE[1:0]
Clock Enables
7 DQS0
37 DQS3
67 VDD
97 VSS
127 VSS
157 VSS
187 VDD
217 DQ52
/CAS
Column Address Strobe
8 VSS
38 VSS
68 NC
98 DQ48 128 DQ6
158 DQ30
188 A0
218 DQ53
/RAS
Row Address Strobe
9 DQ2
39 DQ26
69 VDD
99 DQ49 129 DQ7
159 DQ31
189 VDD
219 VSS
/S[1:0]
Chip Selects
10 DQ3
40 DQ27
70 A10
100 VSS
130 VSS
160 VSS
190 BA1
220 CK2
/WE
Write Enable
11 VSS
41 VSS
71 BA0
101 SA2
131 DQ12
161 CB4 ** 191 VDD
221 /CK2
A[15:0]
Address Inputs
12 DQ8
42 CB0 **
72 VDD
102 NC
132 DQ13
162 CB5 ** 192 /RAS
222 VSS
BA[2:0]
Bank Addresses
13 DQ9
43 CB1 **
73 /WE
103 VSS
133 VSS
163 VSS
193 /S0
223 DM6
ODT[1:0]
On Die Termination Inputs
14 VSS
44 VSS
74 /CAS 104 /DQS6 134 DM1
164 DM8** 194 VDD
224 NC
SA[2:0]
SPD Address
15 /DQS1 45 /DQS8 ** 75 VDD
105 DQS6 135 NC
165 NC
195 ODT0
225 VSS
SCL
SPD Clock Input
16 DQS1
46 DQS8 ** 76 /S1
106 VSS
136 VSS
166 VSS
196 A13
226 DQ54
SDA
SPD Data Input/Output
17 VSS
47 VSS
77 ODT1 107 DQ50 137 CK1
167 CB6 ** 197 VDD
227 DQ55
VSS
Ground
18 NC
48 CB2 **
78 VDD
108 DQ51 138 /CK1
168 CB7 ** 198 VSS
228 VSS
VDD
Power
19 NC
49 CB3 **
79 VSS
109 VSS
139 VSS
169 VSS
199 DQ36
229 DQ60
VDDSPD
SPD EEPROM Power
20 VSS
50 VSS
80 DQ32 110 DQ56 140 DQ14
170 VDD
200 DQ37
230 DQ61
VREF
Reference Voltage
21 DQ10
51 VDD
81 DQ33 111 DQ57 141 DQ15
171 CKE1
201 VSS
231 VSS
NC
No Connection
22 DQ11
52 CKE0
82 VSS
112 VSS
142 VSS
172 VDD
202 DM4
232 DM7
23 VSS
53 VDD
83 /DQS4 113 /DQS7 143 DQ20
173 A15 *
203 NC
233 NC
24 DQ16
54 BA2
84 DQS4 114 DQS7 144 DQ21
174 A14 *
204 VSS
234 VSS
25 DQ17
55 NC
85 VSS
115 VSS
145 VSS
175 VDD
205 DQ38
235 DQ62
26 VSS
56 VDD
86 DQ34 116 DQ58 146 DM2
176 A12
206 DQ39
236 DQ63
27 /DQS2 57 A11
87 DQ35 117 DQ59 147 NC
177 A9
207 VSS
237 VSS
28 DQS2
58 A7
88 VSS
118 VSS
148 VSS
178 VDD
208 DQ44
238 VDDSPD
29 VSS
59 VDD
89 DQ40 119 SDA
149 DQ22
179 A8
209 DQ45
239 SA0
30 DQ18
60 A5
90 DQ41 120 SCL
150 DQ23
180 A6
210 VSS
240 SA1
* Connected but not used
**
Not used Non-ECC DIMM
Identification
DTM63367 256Mx64
Performance range
Clock / Module Speed / CL-t
Performance range
Clock / Module Speed / CL-t
RCD
-t
RP
400 MHz / PC2-6400 / 5-5-5
266 MHz / PC2-4200 / 4-4-4
266 MHz / PC2-4200 / 4-4-4