Dataram DTM63310P ユーザーズマニュアル
DTM63310
1 GB - 128Mx72, 240-Pin Registered DDR2 DIMM
Document 06454, Revision E, 24-MAR-08, Dataram Corporation
© 2008
Page 1
Features
Description
240-pin JEDEC-compliant DIMM
Operating Voltage: 1.8 V ±0.1
I/O Type: SSTL_18
Data Transfer Rate: 400 MHz
Data Bursts: 4 or 8 bits, Sequential or Interleaved ordering
Error Checking and Correction (ECC) bits
Programmable I/O driver strength (OCD)
Programmable On-Die Termination (ODT)
Programmable CAS Latency: 3, 4, or 5
Differential/Single-Ended Data Strobe signals
SDRAM Addressing (Row/Col/Bank): 14/11/2
Fully RoHS Compliant
DTM63310 is a Registered 128Mx72 memory
module which conforms to JEDEC's DDR2,
PC2-3200 standard. The assembly is comprised
of one Rank of eighteen DDR2 DRAMs, two
Registers, one Phase-Locked Loop (PLL), and
one 2K-bit EEPROM used for Serial Presence
Detect.
Both output driver strength and input termination
impedance are programmable to maintain signal
integrity on the I/O signals. Error Checking and
Correction bits are provided to ensure data
integrity. The module will support advanced ECC
features Chipkill and Intel SDDC.
The eighteen Data Strobe signals may be used
either as nine differential pairs, or as eighteen
single-ended strobes for use in systems with a
mix of x4 and x8 DRAMs.
module which conforms to JEDEC's DDR2,
PC2-3200 standard. The assembly is comprised
of one Rank of eighteen DDR2 DRAMs, two
Registers, one Phase-Locked Loop (PLL), and
one 2K-bit EEPROM used for Serial Presence
Detect.
Both output driver strength and input termination
impedance are programmable to maintain signal
integrity on the I/O signals. Error Checking and
Correction bits are provided to ensure data
integrity. The module will support advanced ECC
features Chipkill and Intel SDDC.
The eighteen Data Strobe signals may be used
either as nine differential pairs, or as eighteen
single-ended strobes for use in systems with a
mix of x4 and x8 DRAMs.
Pin Configuration
Pin Description
Front Side
Back Side
Name
Function
1
VREF 31
DQ19 61
A4 91
GND 121
GND 151 GND 181 VDD 211 DQS14
/CAS
Column Address Strobe
2 GND
32 GND
62
VDD 92 /DQS5 122 DQ4
152 DQ28 182 A3
212 /DQS14
/Err_Out*
Parity Error Found
3 DQ0
33 DQ24 63
A2
93 DQS5 123 DQ5
153 DQ29 183 A1
213 GND
/RAS
Row Address Strobe
4
DQ1 34
DQ25 64
VDD 94
GND 124
GND 154 GND 184 VDD 214 DQ46
/RESET
Register and PLL Reset
5 GND
35 GND
65
GND 95 DQ42 125 DQS9 155 DQS12 185 CK0
215 DQ47
/S[1:0] Chip
Selects
6 /DQS0 36 /DQS3 66
GND 96 DQ43 126 /DQS9 156 /DQS12 186 /CK0 216 GND
/WE Write
Enable
7
DQS0 37
DQS3 67
VDD 97
GND 127
GND 157 GND 187 VDD 217 DQ52
A[15:0] Address
Inputs
8 GND
38 GND
68
Par_In*
98 DQ48 128 DQ6
158 DQ30 188 A0
218 DQ53
BA[2:0] Bank
Addresses
9 DQ2
39 DQ26 69
VDD 99 DQ49 129 DQ7
159 DQ31 189 VDD
219 GND
CB[7:0]
Data Check Bits
10 DQ3
40 DQ27
70 A10
100 GND
130 GND
160 GND
190 BA1
220 NC
CK0, /CK0
Differential Clock Inputs
11 GND
41 GND
71 BA0
101 SA2
131 DQ12
161 CB4
191 VDD
221 NC
CKE[1:0] Clock
Enables
12 DQ8
42 CB0
72 VDD
102 NC
132 DQ13
162 CB5
192 /RAS
222 GND
DQ[63:0] Data
Bits
13 DQ9
43 CB1
73 /WE
103 GND
133 GND
163 GND
193 /S0
223 DQS15
DQS[17:0], /DQS[17:0]
Differential Data Strobes
14 GND
44 GND
74 /CAS 104 /DQS6 134 DQS10 164 DQS17 194 VDD
224 /DQS15
GND Ground
15 /DQS1 45 /DQS8
75 VDD
105 DQS6 135 /DQS10 165 /DQS17 195 ODT0
225 GND
NC No
Connection
16 DQS1
46 DQS8
76 /S1
106 GND
136 GND
166 GND
196 A13
226 DQ54
ODT[1:0]
On Die Termination Inputs
17 GND
47 GND
77 ODT1 107 DQ50 137 NC
167 CB6
197 VDD
227 DQ55
Par_In*
Parity Bit, Address & Control
18 /RESET 48 CB2
78 VDD
108 DQ51 138 NC
168 CB7
198 GND
228 GND
SA[2:0] SPD
Address
19 NC
49 CB3
79 GND 109 GND
139 GND
169 GND
199 DQ36
229 DQ60
SCL
SPD Clock Input
20 GND
50 GND
80 DQ32 110 DQ56 140 DQ14
170 VDD
200 DQ37
230 DQ61
SDA
SPD Data Input/Output
21 DQ10
51 VDD
81 DQ33 111 DQ57 141 DQ15
171 CKE1
201 GND
231 GND
VDD Power
22 DQ11
52 CKE0
82 GND 112 GND
142 GND
172 VDD
202 DQS13 232 DQS16
VDDSPD
SPD EEPROM Power
23 GND
53 VDD
83 /DQS4 113 /DQS7 143 DQ20
173 A15
203 /DQS13 233 /DQS16
VREF Reference
Voltage
24 DQ16
54 BA2
84 DQS4 114 DQS7 144 DQ21
174 A14
204 GND
234 GND
25 DQ17
55 /Err_Out* 85 GND 115 GND
145 GND
175 VDD
205 DQ38
235 DQ62
26 GND
56 VDD
86 DQ34 116 DQ58 146 DQS11 176 A12
206 DQ39
236 DQ63
27 /DQS2 57 A11
87 DQ35 117 DQ59 147 /DQS11 177 A9
207 GND
237 GND
28 DQS2
58 A7
88 GND 118 GND
148 GND
178 VDD
208 DQ44
238 VDDSPD
29 GND
59 VDD
89 DQ40 119 SDA
149 DQ22
179 A8
209 DQ45
239 SA0
30 DQ18
60 A5
90 DQ41 120 SCL
150 DQ23
180 A6
210 GND
240 SA1
* = Not Used
Identification
DTM63310 128Mx72
Performance range
Clock / Module Speed / CL-t
Clock / Module Speed / CL-t
RCD
-t
RP
200 MHz / DDR2-400 / 3-3-3