Intel III Xeon 500 MHz 80525KX500512 ユーザーズマニュアル
製品コード
80525KX500512
Pentium
®
III Xeon™ Processor at 500 and 550 MHz
80
Datasheet
8.1.3
Debug Port Signal Descriptions
describes the debug port signals and provides the pin assignment.
Table 44. Debug Port Pinout Description and Requirements
1
(Sheet 1 of 3)
Name
Pin
Description
Specification
Requirement
Notes
RESET#
1
Reset signal from MP
cluster to ITP.
cluster to ITP.
Terminate
2
signal properly
at the debug port
Debug port must be at the
end of the signal trace
end of the signal trace
Connected to high speed
comparator (biased at 2/3 of
the level found at the
POWERON pin) on an ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents if routed properly.
comparator (biased at 2/3 of
the level found at the
POWERON pin) on an ITP
buffer board. Additional load
does not change timing
calculations for the processor
bus agents if routed properly.
DBRESET#
3
Allows ITP to reset
entire target system.
entire target system.
Tie signal to target syste
reset (recommendation:
PWR OK signal on PCIset
as an Ored input
reset (recommendation:
PWR OK signal on PCIset
as an Ored input
Pulled-up signal with the
proper resistor (see notes)
proper resistor (see notes)
Open drain output from ITP to
the target system. It will be
held asserted for 100 ms;
capacitance needs to be small
enough to recognize assert.
The pull-up resistor should be
picked to (1) meet VIL of
target system and (2) meet
specified rise time.
the target system. It will be
held asserted for 100 ms;
capacitance needs to be small
enough to recognize assert.
The pull-up resistor should be
picked to (1) meet VIL of
target system and (2) meet
specified rise time.
TCK
5
The TAP (Test Access
Port) clock from ITP
to MP cluster.
Port) clock from ITP
to MP cluster.
Add 1.0 kW pull-up resistor
to V
to V
CCTAP
near driver
For MP systems, each
processor should receive a
separately buffered TCK.
processor should receive a
separately buffered TCK.
Add a series termination
(UP) resistor or a Bessel
filter (MP) on each output.
(UP) resistor or a Bessel
filter (MP) on each output.
Poor routing can cause
multiple clocking problems.
Should be routed to all
components in the boundary
scan.
multiple clocking problems.
Should be routed to all
components in the boundary
scan.
3
Simulations must be run to
determine proper value fo
series termination (UP) o
Bessel filter (MP)
determine proper value fo
series termination (UP) o
Bessel filter (MP)
TMS
7
Test mode select
signal from ITP to MP
cluster, controls the
TAP finite state
machine.
signal from ITP to MP
cluster, controls the
TAP finite state
machine.
Add 1.0 kW pull-up resistor
to V
to V
CCTAP
near driver
For MP systems, each
processor should receive a
separately buffered TMS.
processor should receive a
separately buffered TMS.
Add a series termination
resistor on each output.
resistor on each output.
Operates synchronously with
TCK. Should be routed to all
components in the boundary
scan.
TCK. Should be routed to all
components in the boundary
scan.
3
Simulations should be run t
determine the proper value for
series termination.
determine the proper value for
series termination.
TDI
8
Test data input signal
from ITP to first
component in
boundary scan chain
of MP cluster; inputs
test instructions and
data serially.
from ITP to first
component in
boundary scan chain
of MP cluster; inputs
test instructions and
data serially.
This signal is open-drain
from an ITP. However, TDI
is pulled up to V
from an ITP. However, TDI
is pulled up to V
CCTAP
with
~150W on the Pentium
®
III
Xeon™ processor. Add a
150 to 330W pull-up
resistor (to V
150 to 330W pull-up
resistor (to V
CCTAP
) if TDI
will not be connected
directly to a processor.
directly to a processor.
Operates synchronously with
TCK.
TCK.
POWERON
9
Used by ITP to
determine when
target system power
is ON and, once
target system is ON,
enables all debug
port electrical
interface activity.
From target V
determine when
target system power
is ON and, once
target system is ON,
enables all debug
port electrical
interface activity.
From target V
TT
to
ITP.
Add 1 kW pull-up resistor
(to VTT)
(to VTT)
If no power is applied, an ITP
will not drive any signals;
isolation provided using
isolation gates. Voltage
applied is internally used to
set AGTL+ threshold (or
reference) at 2/3 V
will not drive any signals;
isolation provided using
isolation gates. Voltage
applied is internally used to
set AGTL+ threshold (or
reference) at 2/3 V
TT
.