Intel i7-3920XM Extreme AW8063801009607 ユーザーズマニュアル
製品コード
AW8063801009607
Processor Configuration Registers
312
Datasheet, Volume 2
33:24
RO
020h
Uncore
Fault-recording Register offset (FRO)
This field specifies the location to the first fault recording register
This field specifies the location to the first fault recording register
relative to the register base address of this remapping hardware
unit.
If the register base address is X, and the value reported in this
If the register base address is X, and the value reported in this
field is Y, the address for the first fault recording register is
calculated as X+(16*Y).
23
RO
0b
Uncore
Isochrony (ISOCH)
0 = Remapping hardware unit has no critical isochronous
0 = Remapping hardware unit has no critical isochronous
requesters in its scope.
1 = Remapping hardware unit has one or more critical
isochronous requesters in its scope. To ensure isochronous
performance, software must ensure invalidation operations
do not impact active DMA streams from such requesters.
This implies, when DMA is active, software performs page-
selective invalidations (and not coarser invalidations).
22
RO
1b
Uncore
Zero Length Read (ZLR)
0 = Indicates the remapping hardware unit blocks (and treats as
0 = Indicates the remapping hardware unit blocks (and treats as
fault) zero length DMA read requests to write-only pages.
1 = Indicates the remapping hardware unit supports zero length
DMA read requests to write-only pages.
DMA remapping hardware implementations are recommended to
report ZLR field as set.
21:16
RO
100110b
Uncore
Maximum Guest Address Width (MGAW)
This field indicates the maximum DMA virtual addressability
This field indicates the maximum DMA virtual addressability
supported by remapping hardware. The Maximum Guest Address
Width (MGAW) is computed as (N+1), where N is the value
reported in this field. For example, a hardware implementation
supporting 48-bit MGAW reports a value of 47 (101111b) in this
field.
If the value in this field is X, untranslated and translated DMA
If the value in this field is X, untranslated and translated DMA
requests to addresses above 2^(x+1)-1 are always blocked by
hardware. Translations requests to address above 2^(x+1)-1
from allowed devices return a null Translation Completion Data
Entry with R=W=0.
Guest addressability for a given DMA request is limited to the
Guest addressability for a given DMA request is limited to the
minimum of the value reported through this field and the
adjusted guest address width of the corresponding page-table
structure. (Adjusted guest address widths supported by
hardware are reported through the SAGAW field).
Implementations are recommended to support MGAW at least
Implementations are recommended to support MGAW at least
equal to the physical addressability (host address width) of the
platform.
15:13
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
8–Fh
Reset Value:
00C9008020660262h
Access:
RO
Size:
64 bits
BIOS Optimal Default
000h
Bit
Access
Reset
Value
RST/
PWR
Description