Intel i7-3920XM Extreme AW8063801009607 ユーザーズマニュアル
製品コード
AW8063801009607
Datasheet, Volume 2
319
Processor Configuration Registers
24
WO
0b
Uncore
Set Interrupt Remap Table Pointer (SIRTP)
This field is valid only for implementations supporting interrupt-
This field is valid only for implementations supporting interrupt-
remapping.
Software sets this field to set/update the interrupt remapping
Software sets this field to set/update the interrupt remapping
table pointer used by hardware. The interrupt remapping table
pointer is specified through the Interrupt Remapping Table
Address (IRTA_REG) register.
Hardware reports the status of the 'Set Interrupt Remap Table
Hardware reports the status of the 'Set Interrupt Remap Table
Pointer’ operation through the IRTPS field in the Global Status
register.
The 'Set Interrupt Remap Table Pointer' operation must be
The 'Set Interrupt Remap Table Pointer' operation must be
performed before enabling or re-enabling (after disabling)
interrupt-remapping hardware through the IRE field.
After a 'Set Interrupt Remap Table Pointer' operation, software
After a 'Set Interrupt Remap Table Pointer' operation, software
must globally invalidate the interrupt entry cache. This is
required to ensure hardware uses only the interrupt-remapping
entries referenced by the new interrupt remap table pointer, and
not any stale cached entries.
While interrupt remapping is active, software may update the
While interrupt remapping is active, software may update the
interrupt remapping table pointer through this field. However, to
ensure valid in-flight interrupt requests are deterministically
remapped, software must ensure that the structures referenced
by the new interrupt remap table pointer are programmed to
provide the same remapping results as the structures referenced
by the previous interrupt remap table pointer.
Clearing this bit has no effect. The value returned on a read of
Clearing this bit has no effect. The value returned on a read of
this field is undefined.
23:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/VC0PREMAP
Address Offset:
18–1Bh
Reset Value:
00000000h
Access:
RO, WO
Size:
32 bits
BIOS Optimal Default
000000h
Bit
Access
Reset
Value
RST/
PWR
Description