AMD Athlon 64 3500+ ADD3500CNBOX 製品データシート
製品コード
ADD3500CNBOX
Advanced Micro Devices
AMD Athlon™ 64 Processor
Product Data Sheet
Product Data Sheet
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Compatible with Existing 32-Bit Code Base
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Including support for SSE, SSE2, SSE3, MMX™,
3DNow!™ technology and legacy x86 instructions
(SSE3 supported by Rev E and later processors)
3DNow!™ technology and legacy x86 instructions
(SSE3 supported by Rev E and later processors)
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Runs existing operating systems and drivers
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Local APIC on-chip
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AMD64 Technology
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AMD64 technology instruction set extensions
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64-bit integer registers, 48-bit virtual addresses, 40-
bit physical addresses
bit physical addresses
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Eight additional 64-bit integer registers (16 total)
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Eight additional 128-bit SSE registers (16 total)
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Cache
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Two 64-bit operations per cycle, 3-cycle latency
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64-Kbyte 2-Way Associative Parity-Protected
L1 Instruction Cache
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L1 Instruction Cache
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With advanced branch prediction
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16-Way Associative ECC-Protected
L2 Cache
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L2 Cache
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Exclusive cache architecture—storage in addition
to L1 caches
to L1 caches
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1 Mbyte, 512-Kbyte and 256-Kbyte options
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Machine Check Architecture
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Includes hardware scrubbing of major
ECC-protected arrays
ECC-protected arrays
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Power Management
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Multiple low-power states
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System Management Mode (SMM)
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ACPI-compliant, including support for processor
performance states
performance states
754-Pin Package Specific Features
•
Refer to the AMD Functional Data Sheet, 754
Pin Package, order# 31410, for functional,
electrical, and mechanical details of 754-pin
package processors.
Pin Package, order# 31410, for functional,
electrical, and mechanical details of 754-pin
package processors.
•
Electrical Interfaces
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–
HyperTransport™ technology: LVDS-like
differential, unidirectional
differential, unidirectional
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DDR SDRAM: SSTL_2 per JEDEC specification
–
Clock, reset, and test signals also use DDR
SDRAM-like electrical specifications
SDRAM-like electrical specifications
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Packaging
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–
754-pin lidded micro PGA
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1.27-mm pin pitch
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29x29-row pin array
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40mm x 40mm organic substrate
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Organic C4 die attach
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Integrated Memory Controller
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Low-latency, high-bandwidth
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72-bit DDR SDRAM at 100, 133, 166, and 200 MHz
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Supports up to three unbuffered DIMMs
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ECC checking with double-bit detect and single-bit
correct
correct
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HyperTransport™ Technology to I/O Devices
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One 16-bit link supporting speeds up to 800 MHz
(1600 MT/s) or 3.2 Gigabytes/s in each direction
(1600 MT/s) or 3.2 Gigabytes/s in each direction
939-Pin Package Specific Features
•
Refer to the AMD Functional Data Sheet, 939
Pin Package, order# 31411, for functional,
electrical, and mechanical details of 939-pin
package processors.
Pin Package, order# 31411, for functional,
electrical, and mechanical details of 939-pin
package processors.
•
Electrical Interfaces
–
–
HyperTransport™ technology: LVDS-like
differential, unidirectional
differential, unidirectional
–
DDR SDRAM: SSTL_2 per JEDEC specification
–
Clock, reset, and test signals also use DDR
SDRAM-like electrical specifications
SDRAM-like electrical specifications
•
Packaging
–
–
939-pin lidded micro PGA
–
1.27-mm pin pitch
–
31x31-row pin array
–
40mm x 40mm organic substrate
–
Organic C4 die attach
•
Integrated Memory Controller
–
–
Low-latency, high-bandwidth
–
144-bit DDR SDRAM at 100, 133, 166, and 200
MHz
MHz
–
Supports up to four unbuffered DIMMs
–
ECC checking with double-bit detect and single-bit
correct
correct
•
HyperTransport™ Technology to I/O Devices
–
–
One 16-bit link supporting speeds up to 1 GHz (2000
MT/s) or 4 Gigabytes/s in each direction
MT/s) or 4 Gigabytes/s in each direction
24659
Publication #
3.12
Revision:
June 2006
Issue Date: