HP A2Y15AV ユーザーズマニュアル
Datasheet, Volume 2
153
Processor Configuration Registers
2.8.7
CLS—Cache Line Size Register
The IGD does not support this register as a PCI slave.
2.8.8
MLT2—Master Latency Timer Register
The IGD does not support the programmability of the master latency timer because it
does not perform bursts.
does not perform bursts.
2.8.9
HDR2—Header Type Register
This register contains the Header Type of the IGD.
B/D/F/Type:
0/2/0/PCI
Address Offset:
Ch
Reset Value:
00h
Access:
RO
Size:
8 bits
Bit
Access
Reset
Value
RST/
PWR
Description
7:0
RO
00h
Uncore
Cache Line Size (CLS)
This field is hardwired to 0s. The IGD as a PCI compliant master
This field is hardwired to 0s. The IGD as a PCI compliant master
does not use the Memory Write and Invalidate command and, in
general, does not perform operations based on cache line size.
B/D/F/Type:
0/2/0/PCI
Address Offset:
Dh
Reset Value:
00h
Access:
RO
Size:
8 bits
Bit
Access
Reset
Value
RST/
PWR
Description
7:0
RO
00h
Uncore
Master Latency Timer Count Value (MLTCV)
Hardwired to 0s.
Hardwired to 0s.
B/D/F/Type:
0/2/0/PCI
Address Offset:
Eh
Reset Value:
00h
Access:
RO
Size:
8 bits
Bit
Access
Reset
Value
RST/
PWR
Description
7
RO
0b
Uncore
Multi Function Status (MFUNC)
This bit indicates if the device is a Multi-Function Device. The
This bit indicates if the device is a Multi-Function Device. The
Value of this register is hardwired to 0; processor graphics is a
single function.
6:0
RO
00h
Uncore
Header Code (H)
This is a 7-bit value that indicates the Header Code for the IGD.
This is a 7-bit value that indicates the Header Code for the IGD.
This code has the value 00h, indicating a type 0 configuration
space format.