HP A2Y15AV ユーザーズマニュアル
Processor Configuration Registers
170
Datasheet, Volume 2
2.10.12 IOBASE—I/O Base Address Register
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
A[11:0] are treated as 0. Thus the bottom of the defined I/O address range will be
aligned to a 4 KB boundary.
2.10.13 IOLIMIT—I/O Limit Address Register
This register controls the processor to PCI Express-G I/O access routing based on the
following formula:
following formula:
IO_BASE ≤ address ≤ IO_LIMIT
Only upper 4 bits are programmable. For the purpose of address decode address bits
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
A[11:0] are assumed to be FFFh. Thus, the top of the defined I/O address range will be
at the top of a 4 KB aligned address block.
B/D/F/Type:
0/6/0/PCI
Address Offset:
1Ch
Reset Value:
F0h
Access:
RW
Size:
8 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
7:4
RW
Fh
Uncore
I/O Address Base (IOBASE:)
This field corresponds to A[15:12] of the I/O addresses passed
This field corresponds to A[15:12] of the I/O addresses passed
by the root port to PCI Express-G
.
3:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/6/0/PCI
Address Offset:
1Dh
Reset Value:
00h
Access:
RW
Size:
8 bits
BIOS Optimal Default
0h
Bit
Access
Reset
Value
RST/
PWR
Description
7:4
RW
0h
Uncore
I/O Address Limit (IOLIMIT)
This field corresponds to A[15:12] of the I/O address limit of the
This field corresponds to A[15:12] of the I/O address limit of the
root port. Devices between this upper limit and IOBASE1 will be
passed to the PCI Express hierarchy associated with this device.
3:0
RO
0h
Reserved (RSVD)