HP A2Y15AV ユーザーズマニュアル
Processor Configuration Registers
258
Datasheet, Volume 2
2.17.1
PM_PDWN_config—Power-down Configuration Register
This register defines the power-down (CKE-off) operation – power-down mode, idle
timer and global / per rank decision.
timer and global / per rank decision.
B/D/F/Type:
0/0/0/MCHBAR_MCBCAST
Address Offset:
4CB0–4CB3h
Reset Value:
00000000h
Access:
RW-L
Size:
32 bits
BIOS Optimal Default
00000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:13
RO
0h
Reserved (RSVD)
12
RW-L
0b
Uncore
Global power-down (GLPDN)
Global Power Down. When this bit is set, the power-down
Global Power Down. When this bit is set, the power-down
decision is global for channel. When this register is clear, a
separate decision is taken for each rank.
11:8
RW-L
0h
Uncore
Power-down mode (PDWN_mode)
Selects the mode of power-down. All encodings not in table are
Selects the mode of power-down. All encodings not in table are
reserved.
Note:
When selecting DLL-off or APD-DLL off, DIMM MR0
register bit 12 (PPD) must equal 0.
Note:
When selecting APD, PPD or APD-PPD DIMM MR0
register bit 12 (PPD) must equal 1.
The value 0h (no power-down) is a don't care.
0h = No Power-Down
1h = APD
2h = PPD
3h = APD+PPD
4h = Reserved
5h = Reserved
6h = PPD_DLLoff
7h = APD+PPD_DLLoff
8h–Fh = Reserved
0h = No Power-Down
1h = APD
2h = PPD
3h = APD+PPD
4h = Reserved
5h = Reserved
6h = PPD_DLLoff
7h = APD+PPD_DLLoff
8h–Fh = Reserved
7:0
RW-L
00h
Uncore
Power-down idle timer (PDWN_idle_counter)
This field defines the rank idle period in DCLK cycles that causes
This field defines the rank idle period in DCLK cycles that causes
power-down entrance.