Intel G550T CM8062301002309 ユーザーズマニュアル
製品コード
CM8062301002309
Processor Configuration Registers
212
Datasheet, Volume 2
2.14.6
TC_RFP_C1—Refresh Parameters Register
2.14.7
TC_RFTP_C1—Refresh Timing Parameters Register
B/D/F/Type:
0/0/0/MCHBAR MC1
Address Offset:
4694–4697h
Default Value:
0000_980Fh
Access:
RW-L
Size:
32 bits
BIOS Optimal Default:
0000h
Bit
Attr
Reset
Value
RST/
PWR
Description
31:18
RO
0h
Reserved
17:16
RW-L
00b
Uncore
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00b = Double refresh rate when DRAM is WARM/HOT.
01b = Force double self refresh regardless of temperature.
10b = Disable double self refresh regardless of temperature.
11b = Reserved
This field will allow the double self refresh enable/disable.
00b = Double refresh rate when DRAM is WARM/HOT.
01b = Force double self refresh regardless of temperature.
10b = Disable double self refresh regardless of temperature.
11b = Reserved
15:12
RW-L
9h
Uncore
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible.
11:8
RW-L
8h
Uncore
Refresh high priority WM (Refresh_HP_WM)
tREFI count level that turns the refresh priority to high (default is
tREFI count level that turns the refresh priority to high (default is
8).
7:0
RW-L
0Fh
Uncore
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
Rank idle period that defines an opportunity for refresh, in DCLK
cycles.
B/D/F/Type:
0/0/0/MCHBAR MC1
Address Offset:
4698–469Bh
Default Value:
46B4_1004h
Access:
RW-L
Size:
32 bits
Bit
Attr
Reset
Value
RST/
PWR
Description
31:25
RW-L
23h
Uncore
9 * tREFI (tREFIx9)
Period of minimum between 9*tREFI and tRAS maximum (normally
Period of minimum between 9*tREFI and tRAS maximum (normally
70 us) in 1024 * DCLK cycles (default is 35) – need to reduce
100 DCLK cycles – uncertainty on timing of panic refresh.
24:16
RW-L
0B4h
Uncore
Refresh execution time (tRFC)
Time of refresh from beginning of refresh until next ACT or refresh
Time of refresh from beginning of refresh until next ACT or refresh
is allowed (in DCLK cycles, default is 180).
15:0
RW-L
1004h
Uncore
tREFI period in DCLK cycles (tREFI)
This field defines the average period between refreshes, and the
This field defines the average period between refreshes, and the
rate that tREFI counter is incremented (in DCLK cycles, default is
4100).